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| To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com Renesas Technology Corp. Customer Support Dept. April 1, 2003 Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. 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Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. Hitachi Single-Chip Microcomputer H8/3297 Series H8/3297 HD6473297, HD6433297 H8/3296 HD6433296 H8/3294 HD6473294, HD6433294 H8/3292 HD6433292 Hardware Manual The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 3rd Edition When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit accoording to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support system. Buyers of Hitachi's products are requested to notify the relevant hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Preface The H8/3297 Series is a series of high-performance microcontrollers with a fast H8/300 CPU core and a set of on-chip supporting functions optimized for embedded control. These include ROM, RAM, three types of timers, a serial communication interface, A/D converter, I/O ports, and other functions needed in control system configurations, so that compact, high-performance systems can be implemented easily. The series includes the H8/3297 with 60-kbyte ROM and 2-kbyte RAM, the H8/3296 with 48-kbyte ROM and 2-kbyte RAM, H8/3294 with 32-kbyte ROM and 1-kbyte RAM, and the H8/3292 with 16-kbyte ROM and 512-byte RAM. The entire H8/3297 Series is available in mask-ROM versions. The H8/3297 and H8/3294 are also available in ZTATTM* (zero turn-around time) versions, providing a quick and flexible response to conditions from ramp-up through full-scale volume production, even for applications with frequently-changing specifications. This manual describes the hardware of the H8/3297 Series. Refer to the H8/300 Series Programming Manual for a detailed description of the instruction set. Note: * ZTATTM is a registered trademark of Hitachi, Ltd. Main Revisions and Additions in this Edition Page 4 14 37, 38 69 71 90 113 133 184 202 to 205 206 223 228 231 254 269 300 to 302 317 340 355 363 364 365 366 367 368 369 Item Table 1-1 Table 1-3 Features Pin Functions Revisions Table amended Table amended Description amended Figure amended Flow amended Description amended Table amended Table amended Description amended Table amended Description amended Whole table replaced Description amended Whole table replaced Figure amended Figure amended Figure amended Note added Note Deleted Table amended Table amended Table amended Figure amended Figure amended Figure amended Figure amended Figure amended Figure amended Figure amended Figure amended Notes on Bit Manipulation Instructions Figure 4-3 Figure 4-4 6.2 Table 7-9 Block Diagram of Interrupt Controller Hardware Interrupt-Handling Sequence Oscillator Circuit (2) Port 4 Pin Functions Table 7-15 Port 7 Register Port 7 Input Register (P7PIN) Bit 7--Overflow Flag (OVF) Bit 6--Timer Mode Select Table 11-3 Table 11-4 Figure 11-11 Figure 11-14 Figure 11-16 13.2.2 15.1.1 Table A-1 B.1 Examples of BRR Settings in Asynchronous Mode (When oP = o) Examples of BRR Settings in Synchronous Mode (When oP = o) Example of SCI Receive Operation Example of SCI Transmit Operation Example of SCI Receive Operation Single-Chip Mode (Mode 3) System Control Register (SYSCR) Instruction Set Addresses TCR--Timer Control Register Figure C-4 (a) Figure C-6 (a) Figure C-6 (b) Figure C-6 (c) Figure C-6 (d) Port 4 Block Diagram (Pin P40) Port 6 Block Diagram (Pin P60) Port 6 Block Diagram (Pin P61) Port 6 Block Diagram (Pin P62) Port 6 Block Diagram (Pins P63 and P65) Figure C-6 (e) Port 6 Block Diagram (Pin P64) Figure C-6 (f) Port 6 Block Diagram (Pin P66) Figure C-6 (g) Port 6 Block Diagram (Pin P67) Contents Section 1 1.1 1.2 1.3 Overview...................................................................................................... Overview ........................................................................................................................ Block Diagram................................................................................................................ Pin Assignments and Functions...................................................................................... 1.3.1 Pin Arrangement............................................................................................. 1.3.2 Pin Functions .................................................................................................. 1 1 5 6 6 9 Section 2 2.1 CPU............................................................................................................... 17 17 17 18 18 19 19 19 20 21 22 23 24 24 26 30 31 33 34 34 36 40 42 43 45 45 46 46 46 47 47 49 2.2 2.3 2.4 2.5 2.6 2.7 Overview ........................................................................................................................ 2.1.1 Features........................................................................................................... 2.1.2 Address Space................................................................................................. 2.1.3 Register Configuration.................................................................................... Register Descriptions...................................................................................................... 2.2.1 General Registers............................................................................................ 2.2.2 Control Registers ............................................................................................ 2.2.3 Initial Register Values .................................................................................... Data Formats................................................................................................................... 2.3.1 Data Formats in General Registers ................................................................. 2.3.2 Memory Data Formats.................................................................................... Addressing Modes .......................................................................................................... 2.4.1 Addressing Mode............................................................................................ 2.4.2 Calculation of Effective Address.................................................................... Instruction Set................................................................................................................. 2.5.1 Data Transfer Instructions .............................................................................. 2.5.2 Arithmetic Operations .................................................................................... 2.5.3 Logic Operations ............................................................................................ 2.5.4 Shift Operations .............................................................................................. 2.5.5 Bit Manipulations ........................................................................................... 2.5.6 Branching Instructions.................................................................................... 2.5.7 System Control Instructions ........................................................................... 2.5.8 Block Data Transfer Instruction ..................................................................... CPU States ...................................................................................................................... 2.6.1 Overview......................................................................................................... 2.6.2 Program Execution State ................................................................................ 2.6.3 Exception-Handling State............................................................................... 2.6.4 Power-Down State .......................................................................................... Access Timing and Bus Cycle........................................................................................ 2.7.1 Access to On-Chip Memory (RAM and ROM) ............................................. 2.7.2 Access to On-Chip Register Field and External Devices ............................... Section 3 3.1 MCU Operating Modes and Address Space..................................... 53 53 53 54 54 56 57 3.2 3.3 3.4 Overview ........................................................................................................................ 3.1.1 Mode Selection ............................................................................................... 3.1.2 Mode and System Control Registers ............................................................. System Control Register (SYSCR)................................................................................. Mode Control Register (MDCR) .................................................................................... Address Space Map in Each Operating Mode................................................................ Section 4 4.1 4.2 Exception Handling.................................................................................. 61 61 61 61 61 64 64 64 66 68 68 69 74 75 76 77 77 77 77 78 78 78 78 80 4.3 4.4 Overview ........................................................................................................................ Reset ........................................................................................................................ 4.2.1 Overview......................................................................................................... 4.2.2 Reset Sequence ............................................................................................... 4.2.3 Disabling of Interrupts after Reset.................................................................. Interrupts ........................................................................................................................ 4.3.1 Overview......................................................................................................... 4.3.2 Interrupt-Related Registers............................................................................. 4.3.3 External Interrupts .......................................................................................... 4.3.4 Internal Interrupts ........................................................................................... 4.3.5 Interrupt Handling .......................................................................................... 4.3.6 Interrupt Response Time................................................................................. 4.3.7 Precaution ....................................................................................................... Note on Stack Handling.................................................................................................. Section 5 5.1 5.2 5.3 Wait-State Controller ............................................................................... Overview ........................................................................................................................ 5.1.1 Features........................................................................................................... 5.1.2 Block Diagram................................................................................................ 5.1.3 Input/Output Pins............................................................................................ 5.1.4 Register Configuration.................................................................................... Register Description ....................................................................................................... 5.2.1 Wait-State Control Register (WSCR)............................................................. Wait Modes..................................................................................................................... Overview ........................................................................................................................ 6.1.1 Block Diagram................................................................................................ 6.1.2 Wait-State Control Register (WSCR)............................................................. Oscillator Circuit ............................................................................................................ Duty Adjustment Circuit................................................................................................. Prescaler ........................................................................................................................ Section 6 6.1 Clock Pulse Generator............................................................................. 83 83 83 84 85 90 90 6.2 6.3 6.4 Section 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 I/O Ports....................................................................................................... 91 Overview ........................................................................................................................ 91 Port 1 ........................................................................................................................ 93 7.2.1 Overview......................................................................................................... 93 7.2.2 Register Configuration and Descriptions........................................................ 94 7.2.3 Pin Functions in Each Mode........................................................................... 96 7.2.4 Input Pull-Up Transistors ............................................................................... 98 Port 2 ........................................................................................................................ 99 7.3.1 Overview......................................................................................................... 99 7.3.2 Register Configuration and Descriptions........................................................ 100 7.3.3 Pin Functions in Each Mode........................................................................... 102 7.3.4 Input Pull-Up Transistors ............................................................................... 105 Port 3 ........................................................................................................................ 106 7.4.1 Overview......................................................................................................... 106 7.4.2 Register Configuration and Descriptions........................................................ 107 7.4.3 Pin Functions in Each Mode........................................................................... 109 7.4.4 Input Pull-Up Transistors ............................................................................... 110 Port 4 ........................................................................................................................ 111 7.5.1 Overview......................................................................................................... 111 7.5.2 Register Configuration and Descriptions........................................................ 112 7.5.3 Pin Functions .................................................................................................. 113 Port 5 ........................................................................................................................ 115 7.6.1 Overview......................................................................................................... 115 7.6.2 Register Configuration and Descriptions........................................................ 115 7.6.3 Pin Functions .................................................................................................. 117 Port 6 ........................................................................................................................ 118 7.7.1 Overview......................................................................................................... 118 7.7.2 Register Configuration and Descriptions........................................................ 119 7.7.3 Pin Functions .................................................................................................. 121 Port 7 ........................................................................................................................ 123 7.8.1 Overview......................................................................................................... 123 7.8.2 Register Configuration and Descriptions........................................................ 124 16-Bit Free-Running Timer ................................................................... 125 Overview ........................................................................................................................ 125 8.1.1 Features........................................................................................................... 125 8.1.2 Block Diagram................................................................................................ 126 8.1.3 Input and Output Pins ..................................................................................... 127 8.1.4 Register Configuration.................................................................................... 127 Register Descriptions...................................................................................................... 128 8.2.1 Free-Running Counter (FRC) ......................................................................... 128 8.2.2 Output Compare Registers A and B (OCRA and OCRB).............................. 129 8.2.3 Input Capture Registers A to D (ICRA to ICRD)........................................... 129 Section 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.2.4 Timer Interrupt Enable Register (TIER)......................................................... 131 8.2.5 Timer Control/Status Register (TCSR) .......................................................... 133 8.2.6 Timer Control Register (TCR)........................................................................ 135 8.2.7 Timer Output Compare Control Register (TOCR)......................................... 137 CPU Interface ................................................................................................................. 139 Operation ........................................................................................................................ 142 8.4.1 FRC Incrementation Timing........................................................................... 142 8.4.2 Output Compare Timing................................................................................. 144 8.4.3 FRC Clear Timing .......................................................................................... 145 8.4.4 Input Capture Timing ..................................................................................... 146 8.4.5 Timing of Input Capture Flag (ICF) Setting................................................... 149 8.4.6 Setting of Output Compare Flags A and B (OCFA and OCFB) .................... 150 8.4.7 Setting of FRC Overflow Flag (OVF) ............................................................ 151 Interrupts ........................................................................................................................ 151 Sample Application ........................................................................................................ 152 Usage Notes .................................................................................................................... 153 Section 9 9.1 9.2 9.3 9.4 9.5 9.6 8-Bit Timers................................................................................................ 159 Overview ........................................................................................................................ 159 9.1.1 Features........................................................................................................... 159 9.1.2 Block Diagram................................................................................................ 160 9.1.3 Input and Output Pins ..................................................................................... 161 9.1.4 Register Configuration.................................................................................... 161 Register Descriptions...................................................................................................... 162 9.2.1 Timer Counter (TCNT)................................................................................... 162 9.2.2 Time Constant Registers A and B (TCORA and TCORB) ............................ 162 9.2.3 Timer Control Register (TCR)........................................................................ 163 9.2.4 Timer Control/Status Register (TCSR) .......................................................... 166 9.2.5 Serial/Timer Control Register (STCR)........................................................... 168 Operation ........................................................................................................................ 169 9.3.1 TCNT Incrementation Timing........................................................................ 169 9.3.2 Compare Match Timing.................................................................................. 171 9.3.3 External Reset of TCNT ................................................................................. 173 9.3.4 Setting of TCSR Overflow Flag (OVF).......................................................... 173 Interrupts ........................................................................................................................ 174 Sample Application ........................................................................................................ 174 Usage Notes .................................................................................................................... 175 9.6.1 Contention between TCNT Write and Clear ................................................. 175 9.6.2 Contention between TCNT Write and Increment .......................................... 176 9.6.3 Contention between TCOR Write and Compare-Match ............................... 177 9.6.4 Contention between Compare-Match A and Compare-Match B ................... 178 9.6.5 Incrementation Caused by Changing of Internal Clock Source ..................... 178 Section 10 10.1 10.2 10.3 10.4 Watchdog Timer ........................................................................................ 181 Overview ........................................................................................................................ 181 10.1.1 Features........................................................................................................... 181 10.1.2 Block Diagram................................................................................................ 182 10.1.3 Register Configuration.................................................................................... 182 Register Descriptions...................................................................................................... 183 10.2.1 Timer Counter (TCNT)................................................................................... 183 10.2.2 Timer Control/Status Register (TCSR) .......................................................... 183 10.2.3 Register Access............................................................................................... 185 Operation ........................................................................................................................ 186 10.3.1 Watchdog Timer Mode................................................................................... 186 10.3.2 Interval Timer Mode....................................................................................... 187 10.3.3 Setting the Overflow Flag............................................................................... 187 Usage Notes .................................................................................................................... 188 10.4.1 Contention between TCNT Write and Increment........................................... 188 10.4.2 Changing the Clock Select Bits (CKS2 to CKS0).......................................... 188 10.4.3 Recovery from Software Standby Mode ........................................................ 188 Serial Communication Interface........................................................... 189 Overview ........................................................................................................................ 189 11.1.1 Features........................................................................................................... 189 11.1.2 Block Diagram................................................................................................ 190 11.1.3 Input and Output Pins ..................................................................................... 191 11.1.4 Register Configuration.................................................................................... 191 Register Descriptions...................................................................................................... 192 11.2.1 Receive Shift Register (RSR) ......................................................................... 192 11.2.2 Receive Data Register (RDR)......................................................................... 192 11.2.3 Transmit Shift Register (TSR)........................................................................ 192 11.2.4 Transmit Data Register (TDR) ....................................................................... 193 11.2.5 Serial Mode Register (SMR) .......................................................................... 193 11.2.6 Serial Control Register (SCR) ........................................................................ 196 11.2.7 Serial Status Register (SSR) ........................................................................... 199 11.2.8 Bit Rate Register (BRR) ................................................................................. 202 11.2.9 Serial/Timer Control Register (STCR)........................................................... 207 Operation ........................................................................................................................ 208 11.3.1 Overview......................................................................................................... 208 11.3.2 Asynchronous Mode....................................................................................... 210 11.3.3 Synchronous Mode ......................................................................................... 224 Interrupts ........................................................................................................................ 233 Usage Notes .................................................................................................................... 233 Section 11 11.1 11.2 11.3 11.4 11.5 Section 12 12.1 A/D Converter............................................................................................ 237 Overview ........................................................................................................................ 237 12.2 12.3 12.4 12.5 12.6 12.1.1 Features........................................................................................................... 237 12.1.2 Block Diagram................................................................................................ 238 12.1.3 Input Pins ........................................................................................................ 239 12.1.4 Register Configuration.................................................................................... 240 Register Descriptions...................................................................................................... 241 12.2.1 A/D Data Registers A to D (ADDRA to ADDRD)........................................ 241 12.2.2 A/D Control/Status Register (ADCSR) .......................................................... 242 12.2.3 A/D Control Register (ADCR) ....................................................................... 244 CPU Interface ................................................................................................................. 245 Operation ........................................................................................................................ 246 12.4.1 Single Mode (SCAN = 0) ............................................................................... 246 12.4.2 Scan Mode (SCAN = 1).................................................................................. 248 12.4.3 Input Sampling and A/D Conversion Time .................................................... 250 12.4.4 External Trigger Input Timing........................................................................ 251 Interrupts ........................................................................................................................ 251 Usage Notes .................................................................................................................... 252 Section 13 13.1 13.2 RAM ............................................................................................................. 253 Overview ........................................................................................................................ 253 13.1.1 Block Diagram................................................................................................ 253 13.1.2 RAM Enable Bit (RAME) in System Control Register (SYSCR) ................. 254 Operation ........................................................................................................................ 254 13.2.1 Expanded Modes (Modes 1 and 2) ................................................................. 254 13.2.2 Single-Chip Mode (Mode 3)........................................................................... 254 ROM.............................................................................................................. 255 Overview ........................................................................................................................ 255 14.1.1 Block Diagram................................................................................................ 256 PROM Mode................................................................................................................... 257 14.2.1 PROM Mode Setup......................................................................................... 257 14.2.2 Socket Adapter Pin Assignments and Memory Map...................................... 257 PROM Programming ...................................................................................................... 260 14.3.1 Programming and Verifying ........................................................................... 260 14.3.2 Notes on Programming ................................................................................... 264 14.3.3 Reliability of Programmed Data..................................................................... 264 14.3.4 Erasing of Data ............................................................................................... 265 Handling of Windowed Packages................................................................................... 266 Power-Down State .................................................................................... 267 Overview ........................................................................................................................ 267 15.1.1 System Control Register (SYSCR)................................................................. 268 Sleep Mode ..................................................................................................................... 269 15.2.1 Transition to Sleep Mode................................................................................ 269 Section 14 14.1 14.2 14.3 14.4 Section 15 15.1 15.2 15.3 15.4 15.2.2 Exit from Sleep Mode..................................................................................... 269 Software Standby Mode ................................................................................................. 270 15.3.1 Transition to Software Standby Mode............................................................ 270 15.3.2 Exit from Software Standby Mode ................................................................. 270 15.3.3 Clock Settling Time for Exit from Software Standby Mode.......................... 271 15.3.4 Sample Application of Software Standby Mode ............................................ 272 15.3.5 Usage Note...................................................................................................... 272 Hardware Standby Mode ................................................................................................ 273 15.4.1 Transition to Hardware Standby Mode........................................................... 273 15.4.2 Recovery from Hardware Standby Mode ....................................................... 273 15.4.3 Timing Relationships...................................................................................... 274 Section 16 16.1 16.2 16.3 Electrical Specifications.......................................................................... 275 Absolute Maximum Ratings ........................................................................................... 275 Electrical Characteristics ................................................................................................ 275 16.2.1 DC Characteristics .......................................................................................... 275 16.2.2 AC Characteristics .......................................................................................... 285 16.2.3 A/D Converter Characteristics........................................................................ 289 MCU Operational Timing............................................................................................... 290 16.3.1 Bus Timing ..................................................................................................... 290 16.3.2 Control Signal Timing .................................................................................... 292 16.3.3 16-Bit Free-Running Timer Timing ............................................................... 294 16.3.4 8-Bit Timer Timing......................................................................................... 295 16.3.5 Serial Communication Interface Timing ........................................................ 296 16.3.6 I/O Port Timing............................................................................................... 297 16.3.7 External Clock Output Timing ....................................................................... 297 Instruction Set List.......................................................................................................... 299 Operation Code Map....................................................................................................... 307 Number of States Required for Execution...................................................................... 309 Appendix A CPU Instruction Set.................................................................................. 299 A.1 A.2 A.3 Appendix B Register Field ............................................................................................. 315 B.1 B.2 Register Addresses and Bit Names................................................................................. 315 Register Descriptions...................................................................................................... 320 Appendix C I/O Port Block Diagrams ........................................................................ 352 C.1 C.2 C.3 C.4 C.5 C.6 C.7 Port 1 Block Diagram ..................................................................................................... Port 2 Block Diagram ..................................................................................................... Port 3 Block Diagram ..................................................................................................... Port 4 Block Diagrams.................................................................................................... Port 5 Block Diagrams.................................................................................................... Port 6 Block Diagrams.................................................................................................... Port 7 Block Diagrams.................................................................................................... 352 353 354 355 360 363 370 Appendix D Pin States ..................................................................................................... 371 D.1 Port States in Each Mode................................................................................................ 371 Appendix E Appendix F Timing of Transition to and Recovery from Hardware Standby Mode.............................................................. 373 Product Code Lineup ............................................................................... 374 Appendix G Package Dimensions ................................................................................ 376 Section 1 Overview 1.1 Overview The H8/3297 Series of single-chip microcomputers features an H8/300 CPU core and a complement of on-chip supporting modules implementing a variety of system functions. The H8/300 CPU is a high-speed processor with an architecture featuring powerful bit-manipulation instructions, ideally suited for realtime control applications. The on-chip supporting modules implement peripheral functions needed in system configurations. These include ROM, RAM, three types of timers (a 16-bit free-running timer, 8-bit timers, and a watchdog timer), a serial communication interface (SCI), an A/D converter, and I/O ports. The H8/3297 Series can operate in single-chip mode or in two expanded modes, depending on the requirements of the application. The entire H8/3297 Series is available with mask ROM. The H8/3297 and H8/3294 are also available in ZTATTM versions* that can be programmed at the user site. Note: * ZTATTM (zero turn-around time) is a trademark of Hitachi, Ltd. Table 1-1 lists the features of the H8/3297 Series. 1 Table 1-1 Features Item CPU Specification Two-way general register configuration * Eight 16-bit registers, or * Sixteen 8-bit registers High-speed operation * Maximum clock rate (o clock): 16 MHz at 5 V, 12 MHz at 4 V or 10 MHz at 3 V * 8- or 16-bit register-register add/subtract: 125 ns (16 MHz), 167 ns (12 MHz), 200 ns (10 MHz) * 8 x 8-bit multiply: 875 ns (16 MHz), 1167 ns (12 MHz), 1400 ns (10 MHz) * 16 / 8-bit divide: 875 ns (16 MHz), 1167 ns (12 MHz), 1400 ns (10 MHz) Streamlined, concise instruction set * Instruction length: 2 or 4 bytes * Register-register arithmetic and logic operations * MOV instruction for data transfer between registers and memory Instruction set features * Multiply instruction (8 bits x 8 bits) * Divide instruction (16 bits / 8 bits) * Bit-accumulator instructions * Register-indirect specification of bit positions Memory * * * * H8/3297: 60k-byte ROM; 2k-byte RAM H8/3296: 48k-byte ROM; 2k-byte RAM H8/3294: 32k-byte ROM; 1k-byte RAM H8/3292: 16k-byte ROM; 512-byte RAM 16-bit freerunning timer (1 channel) 8-bit timer (2 channels) Watchdog timer (WDT) (1 channel) Serial communication interface (SCI) (1 channel) A/D converter * One 16-bit free-running counter (can also count external events) * Two output-compare lines * Four input capture lines (can be buffered) Each channel has * One 8-bit up-counter (can also count external events) * Two time constant registers * Overflow can generate a reset or NMI interrupt * Also usable as interval timer * Asynchronous or synchronous mode (selectable) * Full duplex: can transmit and receive simultaneously * On-chip baud rate generator * * * * 10-bit resolution Eight channels: single or scan mode (selectable) Start of A/D conversion can be externally triggered Sample-and-hold function I/O ports * 43 input/output lines (16 of which can drive LEDs) * 8 input-only lines 2 Table 1-1 Features (cont) Item Interrupts Wait control Operating modes Power-down modes Other features Specification * Four external interrupt lines: NMI, IRQ0 to IRQ2 * 19 on-chip interrupt sources * Three selectable wait modes * Expanded mode with on-chip ROM disabled (mode 1) * Expanded mode with on-chip ROM enabled (mode 2) * Single-chip mode (mode 3) * Sleep mode * Software standby mode * Hardware standby mode * On-chip oscillator 3 Table 1-1 Features (cont) Item Series lineup Specification Part Number 5-V Version (16 MHz) 4-V Version (12 MHz) HD6473297C16 3-V Version (10 MHz) Package HD6473297C16 64-pin windowed shrink DIP (DC-64S) 64-pin shrink DIP (DP-64S) 64-pin QFP (FP-64A) 80-pin TQFP (TFP-80C) 64-pin shrink DIP (DP-64S) 64-pin QFP (FP-64A) Mask ROM ROM PROM Product Name H8/3297 ZTAT HD6473297P16 HD6473297F16 HD6473297TF16 H8/3297 HD6433297P16 HD6433297P12 HD6433297F16 HD6433297F12 HD6433297TF16 HD6433297TF12 H8/3296 HD6433296P16 HD6433296P12 HD6433296F16 HD6433296F12 HD6433296TF16 HD6433296TF12 H8/3294 ZTAT HD6473294P16 HD6473294F16 HD6473294TF16 H8/3294 HD6433294P16 HD6433294P12 HD6433294F16 HD6433294F12 HD6433294TF16 HD6433294TF12 H8/3292 HD6433292P16 HD6433292P12 HD6433292F16 HD6433292F12 HD6433292TF16 HD6433292TF12 HD6473297P16 HD6473297F16 HD6473297TF16 HD6433297VP10 HD6433297VF10 HD6433297VTF10 80-pin TQFP (TFP-80C) HD6433296VP10 HD6433296VF10 64-pin shrink DIP (DP-64S) 64-pin QFP (FP-64A) Mask ROM HD6433296VTF10 80-pin TQFP (TFP-80C) HD6473294P16 HD6473294F16 HD6473294TF16 HD6433294VP10 HD6433294VF10 64-pin shrink DIP (DP-64S) 64-pin QFP (FP-64A) 80-pin TQFP (TFP-80C) 64-pin shrink DIP (DP-64S) 64-pin QFP (FP-64A) Mask ROM PROM HD6433294VTF10 80-pin TQFP (TFP-80C) HD6433292VP10 HD6433292VF10 64-pin shrink DIP (DP-64S) 64-pin QFP (FP-64A) Mask ROM HD6433292VTF10 80-pin TQFP (TFP-80C) 4 1.2 Block Diagram Figure 1-1 shows a block diagram of the H8/3297 Series. XTAL EXTAL Clock pulse generator RES STBY NMI MD0 MD1 VCC VSS CPU H8/300 Address bus Data bus (Low) P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 Data bus (High) Port 1 ROM RAM Watchdog timer Serial communication interface P4 0 /IRQ 2/ADTRG P4 1 /IRQ 1 P4 2 /IRQ 0 P4 3 /RD P4 4 /WR P4 5 /AS P4 6 /O P4 7 /WAIT 8 P20 /A 9 P21 /A P2 /A 2 10 P2 /A 3 11 P2 /A 4 12 P2 /A 5 13 P2 /A 6 14 P2 /A 7 15 16-bit freerunning timer Port 2 Port 4 8-bit timer (2 channels) 10-bit A/D converter (8 channels) P30/D0 P31/D1 P32/D2 P33/D3 P34/D4 P35/D5 P36/D6 P37/D7 Port 6 Port 7 Port 5 P6 /FTCI/TMCI 0 0 P61 /FTOA P6 2 /FTIA 3 P6 /FTIB/TMRI 0 P64 /FTIC/TMO 0 P6 /FTID/TMCI 5 1 P6 /FTOB/TMRI 6 1 P67 /TMO 1 AVCC AVSS /AN 0 /AN 1 /AN 2 /AN 3 /AN 4 /AN 5 /AN 6 7 /AN P5 0 /TxD P5 1 /RxD Figure 1-1 Block Diagram 5 P5 2 /SCK P70 P71 P72 P73 P74 P75 P76 7 P7 Port 3 1.3 Pin Assignments and Functions 1.3.1 Pin Arrangement Figure 1-2 shows the pin arrangement of the DC-64S and DP-64S packages. Figure 1-3 shows the pin arrangement of the FP-64A package. Figure 1-4 shows the pin arrangement of the TFP-80C package. P40/ADTRG/IRQ2 P41/IRQ1 P42/IRQ0 P43/RD P44/WR P45/AS P46/O P47/WAIT P50/TxD P51/RxD P52/SCK RES NMI VCC STBY VSS XTAL EXTAL MD1 MD0 AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVCC P60/FTCI/TMCI0 P61/FTOA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P37/D7 P36/D6 P35/D5 P34/D4 P33/D3 P32/D2 P31/D1 P30/D0 P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 VSS P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 VCC P67/TMO1 P66/FTOB/TMRI1 P65/FTID/TMCI1 P64/FTIC/TMO0 P63/FTIB/TMRI0 P62/FTIA Figure 1-2 Pin Arrangement (DC-64S and DP-64S, Top view) 6 P22/A10 P24/A12 P25/A13 34 48 47 46 45 44 43 42 41 40 39 38 37 36 35 P30/D0 P31/D1 P32/D2 P33/D3 P34/D4 P35/D5 P36/D6 P37/D7 P40/ADTRG/IRQ2 P41/IRQ1 P42/IRQ0 P43/RD P44/WR P45/AS P46/O P47/WAIT 33 P26/A14 P23/A11 P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 P20/A8 P21/A9 VSS 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 10 12 13 14 15 16 11 1 2 3 4 5 6 7 8 9 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P27/A15 VCC P67/TMO1 P66/FTOB/TMRI1 P65/FTID/TMCI1 P64/FTIC/TMO0 P63/FTIB/TMRI0 P62/FTIA P61/FTOA P60/FTCI/TMCI0 AVCC P77/AN7 P76/AN6 P75/AN5 P74/AN4 P73/AN3 P50/TxD P51/RxD NMI XTAL P52/SCK EXTAL STBY VCC MD1 MD0 P70/AN0 P71/AN1 Figure 1-3 Pin Arrangement (FP-64A, Top view) 7 P72/AN2 RES VSS AVSS P22/A10 P23/A11 P24/A12 P25/A13 42 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 P30/D0 P31/D1 P32/D2 P33/D3 P34/D4 VSS P35/D5 P36/D6 P37/D7 VSS P40/ADTRG/IRQ2 P41/IRQ1 VSS P42/IRQ0 P43/RD VSS P44/WR P45/AS P46/O P47/WAIT 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P26/A14 P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 P20/A8 P21/A9 VSS VSS VSS VSS VSS P27/A15 VCC P67/TMO1 P66/FTOB/TMRI1 P65/FTID/TMCI1 P64/FTIC/TMO0 VSS P63/FTIB/TMRI0 P62/FTIA VSS P61/FTOA VSS P60/FTCI/TMCI0 AVCC P77/AN7 P76/AN6 VSS P75/AN5 P74/AN4 P73/AN3 P50/TxD P51/RxD NMI P52/SCK EXTAL STBY XTAL RES MD1 MD0 P70/AN0 P71/AN1 Figure 1-4 Pin Arrangement (TFP-80C, Top view) 8 P72/AN2 VSS VSS VSS VSS VSS AVSS VCC 1.3.2 Pin Functions (1) Pin Assignments in Each Operating Mode: Table 1-2 lists the assignments of the pins of the DC-64S, DP-64S, FP-64A, and TFP-80C packages in each operating mode. Table 1-2 Pin Assignments in Each Operating Mode Pin No. DC-64S DP-64S FP-64A TFP-80C Mode 1 1 2 -- 3 4 -- 5 6 7 8 9 10 11 12 13 14 15 16 -- -- 17 -- 18 19 57 58 -- 59 60 -- 61 62 63 64 1 2 3 4 5 6 7 8 -- -- 9 -- 10 11 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Expanded modes Mode 2 Single-chip mode PROM Mode 3 mode P40/IRQ2/ADTRG P40/IRQ2/ADTRG P40/IRQ2/ADTRG EA16 P41/IRQ1 VSS P42/IRQ0 RD VSS WR AS O P47/WAIT P50/TxD P51/RxD P52/SCK RES NMI VCC STBY VSS VSS VSS XTAL VSS EXTAL MD1 P41/IRQ1 VSS P42/IRQ0 RD VSS WR AS O P47/WAIT P50/TxD P51/RxD P52/SCK RES NMI VCC STBY VSS VSS VSS XTAL VSS EXTAL MD1 P41/IRQ1 VSS P42/IRQ0 P43 VSS P44 P45 P46/O P47 P50/TxD P51/RxD P52/SCK RES NMI VCC STBY VSS VSS VSS XTAL VSS EXTAL MD1 EA15 VSS PGM NC VSS NC NC NC NC NC NC NC VPP EA9 VCC VSS VSS VSS VSS NC VSS NC VSS Note: Pins marked NC should be left unconnected. For details on PROM mode, refer to 14.2, PROM Mode. 9 Table 1-2 Pin Assignments in Each Operating Mode (cont) Pin No. DC-64S DP-64S FP-64A TFP-80C Mode 1 -- 20 21 22 23 24 25 26 27 -- 28 29 30 31 -- 32 -- 33 34 -- 35 36 37 38 39 40 41 42 -- 12 13 14 15 16 17 18 19 -- 20 21 22 23 -- 24 -- 25 26 -- 27 28 29 30 31 32 33 34 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 VSS MD0 AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 VSS P76/AN6 P77/AN7 AVCC P60/FTCI/TMCI0 VSS P61/FTOA VSS P62/FTIA P63/FTIB/TMRI0 VSS P64/FTIC/TMO0 P65/FTID/TMCI1 P66/FTOB/TMRI1 P67/TMO1 VCC A15 A14 A13 Expanded modes Mode 2 VSS MD0 AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 VSS P76/AN6 P77/AN7 AVCC P60/FTCI/TMCI0 VSS P61/FTOA VSS P62/FTIA P63/FTIB/TMRI0 VSS P64/FTIC/TMO0 P65/FTID/TMCI1 P66/FTOB/TMRI1 P67/TMO1 VCC A27/A15 P26/A14 P25/A13 Single-chip mode PROM Mode 3 VSS MD0 AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 VSS P76/AN6 P77/AN7 AVCC P60/FTCI/TMCI0 VSS P61/FTOA VSS P62/FTIA P63/FTIB/TMRI0 VSS P64/FTIC/TMO0 P65/FTID/TMCI1 P66/FTOB/TMRI1 P67/TMO1 VCC P27 P26 P25 mode VSS VSS VSS NC NC NC NC NC NC VSS NC NC VCC NC VSS NC VSS NC VCC VSS VCC NC NC NC VCC CE EA14 EA13 Note: Pins marked NC should be left unconnected. For details on PROM mode, refer to 14.2, PROM Mode. 10 Table 1-2 Pin Assignments in Each Operating Mode (cont) Pin No. DC-64S DP-64S FP-64A TFP-80C Mode 1 43 44 -- 45 46 47 -- 48 -- 49 50 51 -- 52 53 54 55 56 57 58 59 60 61 -- 62 63 64 -- 35 36 -- 37 38 39 -- 40 -- 41 42 43 -- 44 45 46 47 48 49 50 51 52 53 -- 54 55 56 -- 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 A12 A11 VSS A10 A9 A8 VSS VSS VSS A7 A6 A5 VSS A4 A3 A2 A1 A0 D0 D1 D2 D3 D4 VSS D5 D6 D7 VSS Expanded modes Mode 2 P24/A12 P23/A11 VSS P22/A10 P21/A9 P20/A8 VSS VSS VSS P17/A7 P16/A6 P15/A5 VSS P14/A4 P13/A3 P12/A2 P11/A1 P10/A0 D0 D1 D2 D3 D4 VSS D5 D6 D7 VSS Single-chip mode PROM Mode 3 P24 P23 VSS P22 P21 P20 VSS VSS VSS P17 P16 P15 VSS P14 P13 P12 P11 P10 P30 P31 P32 P33 P34 VSS P35 P36 P37 VSS mode EA12 EA11 VSS EA10 OE EA8 VSS VSS VSS EA7 EA6 EA5 VSS EA4 EA3 EA2 EA1 EA0 EO0 EO1 EO2 EO3 EO4 VSS EO5 EO6 EO7 VSS Note: Pins marked NC should be left unconnected. For details on PROM mode, refer to 14.2, PROM Mode. 11 (2) Pin Functions: Table 1-3 gives a concise description of the function of each pin. Table 1-3 Pin Functions Pin No. Type Power Symbol VCC DC-64S DP-64S FP-64A 14, 39 6, 31 TFP-80C 6, 39 I/O Name and function I Power: Connected to the power supply (+5 V or +3 V). Connect both VCC pins to the system power supply (+5 V or +3 V). Ground: Connected to ground (0 V). Connect all VSS pins to system ground (0 V). VSS 16, 48 8, 40 8, 9, 10, I 12, 15, 24, 29, 31, 34, 45, 49, 50, 51, 55, 66, 70, 73, 76 11 I Clock XTAL 17 9 Crystal: Connected to a crystal oscillator. The crystal frequency should be the same as the desired system clock frequency. If an external clock is input at the EXTAL pin, a reverse-phase clock should be input at the XTAL pin. External crystal: Connected to a crystal oscillator or external clock. The frequency of the external clock should be the same as the desired system clock frequency. See section 6.2, Oscillator Circuit for examples of connections to a crystal and external clock. System clock: Supplies the system clock to peripheral devices. Reset: A Low input causes the chip to reset. Standby: A transition to the hardware standby mode (a power-down state) occurs when a Low input is received at the STBY pin. Address bus: Address output pins. EXTAL 18 10 13 I o System control RES STBY 7 12 15 63 4 7 79 4 7 O I I Address bus A15 to A0 40 to 47, 32 to 39, 40 to 44, 49 to 56 41 to 48 46 to 48, 52 to 54, 56 to 60 O 12 Table 1-3 Pin Functions (cont) Pin No. Type Data bus Bus control Symbol D7 to D0 WAIT DC-64S DP-64S FP-64A TFP-80C I/O Name and function I/O Data bus: 8-Bit bidirectional data bus. I Wait: Requests the CPU to insert wait states into the bus cycle when an external address is accessed. Read: Goes Low to indicate that the CPU is reading an external address. Write: Goes Low to indicate that the CPU is writing to an external address. Address strobe: Goes Low to indicate that there is a valid address on the address bus. Nonmaskable interrupt: Highestpriority interrupt request. The NMIEG bit in the system control register (SYSCR) determines whether the interrupt is recognized at the rising or falling edge of the NMI input. Interrupt request 0 to 2: Maskable interrupt request pins. Mode: Input pins for setting the MCU operating mode according to the table below. MD1 MD0 Mode 0 1 Description 64 to 57 56 to 49 65 to 61, 69 to 67 8 64 80 RD WR AS 4 5 6 60 61 62 75 77 78 O O O Interrupt signals NMI 13 5 5 I IRQ0 to IRQ2 Operating mode control MD1, MD0 1 to 3 19, 20 57 to 59 71, 72, 74 11, 12 14, 16 I I Mode 1 Expanded mode with on-chip ROM disabled Mode 2 Expanded mode with on-chip ROM enabled Mode 3 Single-chip mode 1 0 1 1 13 Table 1-3 Pin Functions (cont) Pin No. Type Symbol DC-64S DP-64S FP-64A 32, 37 31 24, 29 23 TFP-80C 30, 37 28 I/O Name and function O FRT output compare A and B: Output pins controlled by comparators A and B of the free-running timer. FRT counter clock input: Input pin for an external clock signal for the free-running timer. FRT input capture A to D: Input capture pins for the free-running timer. 8-bit timer output (channels 0 and 1): Compare-match output pins for the 8-bit timers. 8-bit timer counter clock input (channels 0 and 1): External clock input pins for the 8-bit timer counters. 8-bit timer counter reset input (channels 0 and 1): A High input at these pins resets the 8-bit timer counters. Transmit data: Data output pin for the serial communication interface. Receive data: Data input pin for the serial communication interface. 16-bit free- FTOA, running FTOB timer (FRT) FTCI I FTIA to FTID 8-bit timer TMO0, TMO1 TMCI0, TMCI1 TMRI0, TMRI1 33 to 36 25 to 28 32, 33, 35, I 36 35, 38 31, 36 34, 37 27, 30 23, 28 26, 29 35, 38 28, 36 33, 37 O I I Serial communication interface (SCI) TxD RxD SCK 9 10 11 1 2 3 1 2 3 O I I/O Serial clock: Input/output pin for the serial clock. I I I Analog input: Analog signal input pins for the A/D converter. A/D trigger: External trigger input for starting the A/D converter. Programmable Wait Mode: The number of wait states (TW) selected by bits WC1 and WC0 are inserted in all accesses to external addresses, regardless of the WAIT pin state. Analog ground: Ground pin for the A/D converter. Connect to system ground. A/D converter AN7 to AN0 29 to 22 21 to 14 26, 25, 23 to 18 ADTRG AVCC 1 30 57 22 71 27 AVSS 21 13 17 I 14 Table 1-3 Pin Functions (cont) Pin No. Type Generalpurpose I/O Symbol DC-64S DP-64S FP-64A TFP-80C I/O Name and function I/O Port 1: An 8-bit input/output port with programmable MOS input pull-ups and LED driving capability. The direction of each bit can be selected in the port 1 data direction register (P1DDR). I/O Port 2: An 8-bit input/output port with programmable MOS input pull-ups and LED driving capability. The direction of each bit can be selected in the port 2 data direction register (P2DDR). I/O Port 3: An 8-bit input/output port with programmable MOS input pull-ups. The direction of each bit can be selected in the port 3 data direction register (P3DDR). P17 to P10 49 to 56 41 to 48 52 to 54, 56 to 60 P27 to P20 40 to 47 32 to 39 40 to 44, 46 to 48 P37 to P30 64 to 57 56 to 49 69 to 67, 65 to 61 P47 to P40 8 to 1 64 to 57 80 to 77 I/O Port 4: An 8-bit input/output port. The 75, 74, 72, direction of each bit can be selected 71 in the port 4 data direction register (P4DDR). 3 to 1 3 to 1 I/O Port 5: A 3-bit input/output port. The direction of each bit can be selected in the port 5 data direction register (P5DDR). P52 to P50 11 to 9 I/O Port 6: An 8-bit input/output port. The P67 to P60 38 to 31 30 to 23 38 to 35, 33, 32, 30, direction of each bit can be selected 28 in the port 6 data direction register (P6DDR). P77 to P70 29 to 22 21 to 14 26, 25, 23 to 18 I Port 7: An 8-bit input port. 15 16 Section 2 CPU 2.1 Overview The H8/300 CPU is a fast central processing unit with eight 16-bit general registers (also configurable as 16 eight-bit registers) and a concise instruction set designed for high-speed operation. 2.1.1 Features The main features of the H8/300 CPU are listed below. * Two-way register configuration -- Sixteen 8-bit general registers, or -- Eight 16-bit general registers * Instruction set with 57 basic instructions, including: -- Multiply and divide instructions -- Powerful bit-manipulation instructions * Eight addressing modes -- -- -- -- -- -- -- -- * * Register direct (Rn) Register indirect (@Rn) Register indirect with displacement (@(d:16, Rn)) Register indirect with post-increment or pre-decrement (@Rn+ or @-Rn) Absolute address (@aa:8 or @aa:16) Immediate (#xx:8 or #xx:16) PC-relative (@(d:8, PC)) Memory indirect (@@aa:8) Maximum 64-kbyte address space High-speed operation -- All frequently-used instructions are executed in two to four states * Maximum clock rate (o clock): 16 MHz at 5 V, 12 MHz at 4 V or 10 MHz at 3 V -- 8- or 16-bit register-register add or subtract: 125 ns (16 MHz), 167 ns (12 MHz), 200 ns (10 MHz) -- 8 x 8-bit multiply: 875 ns (16 MHz), 1167 ns (12 MHz), 1400 ns (10 MHz) -- 16 / 8-bit divide: 875 ns (16 MHz), 1167 ns (12 MHz), 1400 ns (10 MHz) * Power-down mode -- SLEEP instruction 17 2.1.2 Address Space The H8/300 CPU supports an address space with a maximum size of 64 kbytes for program code and data combined. The memory map differs depending on the mode (mode 1, 2, or 3). For details, see section 3.4, Address Space Map in Each Operating Mode. 2.1.3 Register Configuration Figure 2-1 shows the internal register structure of the H8/300 CPU. There are two groups of registers: the general registers and control registers. General registers (Rn) 7 R0H R1H R2H R3H R4H R5H R6H R7H (SP) 07 R0L R1L R2L R3L R4L R5L R6L R7L SP: Stack pointer 0 Control registers 15 PC 76543210 I UHUNZVC 0 PC: Program counter CCR: Condition code register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask bit User bit User bit CCR Figure 2-1 CPU Registers 18 2.2 Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). When used as data registers, they can be accessed as 16-bit registers, or the high and low bytes can be accessed separately as 8-bit registers (R0H to R7H and R0L to R7L). R7 also functions as the stack pointer, used implicitly by hardware in processing interrupts and subroutine calls. In assembly-language coding, R7 can also be denoted by the letters SP. As indicated in figure 2-2, R7 (SP) points to the top of the stack. Unused area SP (R7) Stack area Figure 2-2 Stack Pointer 2.2.2 Control Registers The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code register (CCR). (1) Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute. Each instruction is accessed in 16 bits (1 word), so the least significant bit of the PC is ignored (always regarded as 0). (2) Condition Code Register (CCR): This 8-bit register contains internal status information, including carry (C), overflow (V), zero (Z), negative (N), and half-carry (H) flags and the interrupt mask bit (I). Bit 7--Interrupt Mask Bit (I): When this bit is set to 1, all interrupts except NMI are masked. This bit is set to 1 automatically by a reset and at the start of interrupt handling. 19 Bit 6--User Bit (U): This bit can be written and read by software (using the LDC, STC, ANDC, ORC, and XORC instructions). Bit 5--Half-Carry Flag (H): This flag is set to 1 when the ADD.B, ADDX.B, SUB.B, SUBX.B, NEG.B, or CMP.B instruction causes a carry or borrow out of bit 3, and is cleared to 0 otherwise. Similarly, it is set to 1 when the ADD.W, SUB.W, or CMP.W instruction causes a carry or borrow out of bit 11, and cleared to 0 otherwise. It is used implicitly in the DAA and DAS instructions. Bit 4--User Bit (U): This bit can be written and read by software (using the LDC, STC, ANDC, ORC, and XORC instructions). Bit 3--Negative Flag (N): This flag indicates the most significant bit (sign bit) of the result of an instruction. Bit 2--Zero Flag (Z): This flag is set to 1 to indicate a zero result and cleared to 0 to indicate a nonzero result. Bit 1--Overflow Flag (V): This flag is set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry Flag (C): This flag is used by: * Add and subtract instructions, to indicate a carry or borrow at the most significant bit of the result Shift and rotate instructions, to store the value shifted out of the most significant or least significant bit Bit manipulation and bit load instructions, as a bit accumulator * * The LDC, STC, ANDC, ORC, and XORC instructions enable the CPU to load and store the CCR, and to set or clear selected bits by logic operations. The N, Z, V, and C flags are used in conditional branching instructions (BCC). For the action of each instruction on the flag bits, see the H8/300 Series Programming Manual. 2.2.3 Initial Register Values When the CPU is reset, the program counter (PC) is loaded from the vector table and the interrupt mask bit (I) in the CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (R7) is not initialized. The stack pointer and CCR should be initialized by software, by the first instruction executed after a reset. 20 2.3 Data Formats The H8/300 CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. * Bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a byte operand. All arithmetic and logic instructions except ADDS and SUBS can operate on byte data. The DAA and DAS instruction perform decimal arithmetic adjustments on byte data in packed BCD form. Each nibble of the byte is treated as a decimal digit. The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions operate on word data. * * * 21 2.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2-3. Data Type Register No. 7 Data Format 0 1-bit data RnH 7 6 5 4 3 2 1 0 Don't care 7 0 1-bit data RnL Don't care 7 6 5 4 3 2 1 0 7 0 LSB Byte data RnH MSB Don't care 7 0 LSB Byte data RnL Don't care MSB 15 0 LSB Word data Rn MSB 7 4 Upper digit 3 Lower digit 0 4-bit BCD data RnH Don't care 7 4 Upper digit 3 Lower digit 0 4-bit BCD data RnL Don't care Legend RnH: Upper digit of general register RnL: Lower digit of general register MSB: Most significant bit LSB: Least significant bit Figure 2-3 Register Data Formats 22 2.3.2 Memory Data Formats Figure 2-4 indicates the data formats in memory. Word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as 0. If an odd address is specified, no address error occurs but the access is performed at the preceding even address. This rule affects MOV.W instructions and branching instructions, and implies that only even addresses should be stored in the vector table. Data Type Address Data Format 7 0 1-bit data Byte data Address n Address n Even address Odd address Even address Odd address Even address Odd address 7 MSB 6 5 4 3 2 1 0 LSB Word data MSB Upper 8 bits Lower 8 bits LSB Byte data (CCR) on stack MSB MSB CCR CCR* LSB LSB Word data on stack MSB LSB Note: * Ignored on return Legend CCR: Condition code register Figure 2-4 Memory Data Formats When the stack is addressed by register R7, it must always be accessed a word at a time. When the CCR is pushed on the stack, two identical copies of the CCR are pushed to make a complete word. When they are restored, the lower byte is ignored. 23 2.4 Addressing Modes 2.4.1 Addressing Mode The H8/300 CPU supports eight addressing modes. Each instruction uses a subset of these addressing modes. Table 2-1 Addressing Modes No. (1) (2) (3) (4) (5) (6) (7) (8) Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter-relative Memory indirect Symbol Rn @Rn @(d:16, Rn) @Rn+ @-Rn @aa:8 or @aa:16 #xx:8 or #xx:16 @(d:8, PC) @@aa:8 (1) Register Direct--Rn: The register field of the instruction specifies an 8- or 16-bit general register containing the operand. In most cases the general register is accessed as an 8-bit register. Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions have 16-bit operands. (2) Register Indirect--@Rn: The register field of the instruction specifies a 16-bit general register containing the address of the operand. (3) Register Indirect with Displacement--@(d:16, Rn): This mode, which is used only in MOV instructions, is similar to register indirect but the instruction has a second word (bytes 3 and 4) which is added to the contents of the specified general register to obtain the operand address. For the MOV.W instruction, the resulting address must be even. (4) Register Indirect with Post-Increment or Pre-Decrement--@Rn+ or @-Rn: * Register indirect with Post-Increment--@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. It is similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is incremented after the operand is accessed. The size of the increment is 1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even. 24 * Register Indirect with Pre-Decrement--@-Rn The @-Rn mode is used with MOV instructions that store register contents to memory. It is similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is decremented before the operand is accessed. The size of the decrement is 1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even. (5) Absolute Address--@aa:8 or @aa:16: The instruction specifies the absolute address of the operand in memory. The MOV.B instruction uses an 8-bit absolute address of the form H'FFxx. The upper 8 bits are assumed to be 1, so the possible address range is H'FF00 to H'FFFF (65280 to 65535). The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses. (6) Immediate--#xx:8 or #xx:16: The instruction contains an 8-bit operand in its second byte, or a 16-bit operand in its third and fourth bytes. Only MOV.W instructions can contain 16-bit immediate values. The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit manipulation instructions contain 3-bit immediate data (#xx:3) in the second or fourth byte of the instruction, specifying a bit number. (7) Program-Counter-Relative--@(d:8, PC): This mode is used to generate branch addresses in the Bcc and BSR instructions. An 8-bit value in byte 2 of the instruction code is added as a signextended value to the program counter contents. The result must be an even number. The possible branching range is -126 to +128 bytes (-63 to +64 words) from the current address. (8) Memory Indirect--@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address from H'0000 to H'00FF (0 to 255). The word located at this address contains the branch address. The upper 8 bits of the absolute address are 0 (H'00), thus the branch address is limited to values from 0 to 255 (H'0000 to H'00FF). Note that some of the addresses in this range are also used in the vector table. Refer to section 3.4, Address Space Map in Each Operating Mode. If an odd address is specified as a branch destination or as the operand address of a MOV.W instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. See section 2.3.2, Memory Data Formats, for further information. 25 2.4.2 Calculation of Effective Address Table 2-2 shows how the H8/300 calculates effective addresses in each addressing mode. Arithmetic, logic, and shift instructions use register direct addressing (1). The ADD.B, ADDX.B, SUBX.B, CMP.B, AND.B, OR.B, and XOR.B instructions can also use immediate addressing (6). The MOV instruction uses all the addressing modes except program-counter relative (7) and memory indirect (8). Bit manipulation instructions use register direct (1), register indirect (2), or 8-bit absolute (5) addressing to identify a byte operand, and 3-bit immediate addressing to identify a bit within the byte. The BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing (1) to identify the bit. 26 Table 2-2 Effective Address Calculation Effective Address Calculation 3 0 3 No. regm 43 0 Addressing Mode and Instruction Format Effective Address 0 1 Register direct, Rn regn 15 87 op 15 0 regm regn Operands are contained in registers regm and regn 16-bit register contents 15 2 43 0 Register indirect, @Rn 0 15 76 op 15 0 reg 16-bit register contents disp 3 43 0 Register indirect with displacement, @(d:16, Rn) reg 15 0 27 15 15 76 op disp 0 15 0 4 43 0 Register indirect with post-increment, @Rn+ reg 16-bit register contents 15 76 op 15 1 or 2 * 0 Register indirect with pre-decrement, @-Rn 43 0 16-bit register contents 15 0 15 76 op reg 1 or 2 * Note: * 1 for a byte operand, 2 for a word operand Table 2-2 Effective Address Calculation (cont) Effective Address Calculation 15 87 No. H'FF 0 Addressing Mode and Instruction Format Effective address 5 Absolute address @aa:8 abs 15 0 0 15 87 op @aa:16 0 15 op abs 6 0 Immediate #xx:8 IMM Operand is 1- or 2-byte immediate data 0 28 15 15 87 op #xx:16 15 op IMM 0 7 PC-relative @(d:8, PC) PC contents 15 0 15 87 0 Sign extension disp op disp Table 2-2 Effective Address Calculation (cont) Effective Address Calculation Effective Address No. Addressing Mode and Instruction Format 8 0 Memory indirect, @@aa:8 15 87 op 15 87 0 abs H'00 15 0 Memory contents (16 bits) 29 Legend reg: General register op: Operation code disp: Displacement IMM: Immediate data abs: Absolute address 2.5 Instruction Set The H8/300 CPU has 57 types of instructions, which are classified by function in table 2-3. Table 2-3 Instruction Classification Function Data transfer Arithmetic operations Logic operations Shift Bit manipulation Branch System control Block data transfer Instructions MOV, MOVTPE*3, MOVFPE*3, PUSH*1, POP*1 ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc*2, JMP, BSR, JSR, RTS RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP EEPMOV Types 3 14 4 8 14 5 8 1 Total 57 Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @-SP. POP Rn is equivalent to MOV.W @SP+, Rn. 2. Bcc is a conditional branch instruction in which cc represents a condition code. 3. Not supported by the H8/3297 Series. The following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. The notation used is defined next. Operation Notation Rd Rs Rn (EAd) (EAs) SP PC CCR N Z V C #imm General register (destination) General register (source) General register Destination operand Source operand Stack pointer Program counter Condition code register N (negative) flag of CCR Z (zero) flag of CCR V (overflow) flag of CCR C (carry) flag of CCR Immediate data #xx:3 #xx:8 #xx:16 disp + - x / 3-Bit immediate data 8-Bit immediate data 16-Bit immediate data Displacement Addition Subtraction Multiplication Division AND logical OR logical Exclusive OR logical Move Not 30 2.5.1 Data Transfer Instructions Table 2-4 describes the data transfer instructions. Figure 2-5 shows their object code formats. Table 2-4 Data Transfer Instructions Instruction MOV Size* B/W Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:8 or #xx:16, @-Rn, and @Rn+ addressing modes are available for byte or word data. The @aa:8 addressing mode is available for byte data only. The @-R7 and @R7+ modes require word operands. Do not specify byte size for these two modes. Not supported by the H8/3437 Series. Not supported by the H8/3437 Series. Rn @-SP Pushes a 16-bit general register onto the stack. Equivalent to MOV.W Rn, @-SP. @SP+ Rn Pops a 16-bit general register from the stack. Equivalent to MOV.W @SP+, Rn. MOVTPE MOVFPE PUSH B B W POP W Note: * Size: Operand size B: Byte W: Word 31 15 8 7 0 MOV RmRn op 15 8 7 rm rn 0 op 15 8 7 rm rn 0 @RmRn op disp 15 8 7 rm rn @(d:16, Rm)Rn 0 op 15 8 7 rm rn 0 @Rm+Rn, or Rn@-Rm op 15 rn 8 7 abs 0 @aa:8Rn op abs 15 8 7 rn @aa:16Rn 0 op 15 rn 8 7 IMM 0 #xx:8Rn op IMM 15 8 7 rn #xx:16Rn 0 op abs 15 8 7 rn MOVFPE, MOVTPE 0 op Legend op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data rn POP, PUSH Figure 2-5 Data Transfer Instruction Codes 32 2.5.2 Arithmetic Operations Table 2-5 describes the arithmetic instructions. See figure 2-6 in section 2.5.4, Shift Operations, for their object codes. Table 2-5 Arithmetic Instructions Instruction ADD SUB Size* B/W Function Rd Rs Rd, Rd + #imm Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register. Word data can be added or subtracted only when both words are in general registers. Rd Rs C Rd, Rd #imm C Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or addition or subtraction on immediate data and data in a general register. Rd #1 Rd Increments or decrements a general register. Rd #imm Rd Adds or subtracts immediate data to or from data in a general register. The immediate data must be 1 or 2. Rd decimal adjust Rd Decimal-adjusts (adjusts to packed BCD) an addition or subtraction result in a general register by referring to the CCR. Rd x Rs Rd Performs 8-bit 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result. Rd / Rs Rd Performs 16-bit / 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder. Rd - Rs, Rd - #imm Compares data in a general register with data in another general register or with immediate data. Word data can be compared only between two general registers. 0 - Rd Rd Obtains the two's complement (arithmetic complement) of data in a general register. ADDX SUBX B INC DEC ADDS SUBS DAA DAS MULXU B W B B DIVXU B CMP B/W NEG B Note: * Size: Operand size B: Byte W: Word 33 2.5.3 Logic Operations Table 2-6 describes the four instructions that perform logic operations. See figure 2-6 in section 2.5.4, Shift Operations, for their object codes. Table 2-6 Logic Operation Instructions Instruction AND Size* B Function Rd Rs Rd, Rd #imm Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #imm Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #imm Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. (Rd) (Rd) Obtains the one's complement (logical complement) of general register contents. OR B XOR B NOT B Note: * Size: Operand size B: Byte 2.5.4 Shift Operations Table 2-7 describes the eight shift instructions. Figure 2-6 shows the object code formats of the arithmetic, logic, and shift instructions. Table 2-7 Shift Instructions Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Size* B B B B Function Rd shift Rd Performs an arithmetic shift operation on general register contents. Rd shift Rd Performs a logical shift operation on general register contents. Rd rotate Rd Rotates general register contents. Rd rotate through carry Rd Rotates general register contents through the C (carry) bit. Note: * Size: Operand size B: Byte 34 15 8 7 0 op 15 8 7 rm rn 0 ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT 0 op 15 8 7 rn op 15 8 7 rm rn 0 MULXU, DIVXU op 15 rn 8 7 IMM 0 ADD, ADDX, SUBX, CMP (#xx:8) op 15 8 7 rm rn 0 AND, OR, XOR (Rm) op 15 rn 8 7 IMM 0 AND, OR, XOR (#xx:8) op Legend op: Operation field rm, rn: Register field IMM: Immediate data rn SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR Figure 2-6 Arithmetic, Logic, and Shift Instruction Codes 35 2.5.5 Bit Manipulations Table 2-8 describes the bit-manipulation instructions. Figure 2-7 shows their object code formats. Table 2-8 Bit-Manipulation Instructions Instruction BSET Size* B Function 1 ( BCLR B BNOT B BTST B BAND BIAND B BOR BIOR BXOR Note: * Size: Operand size B: Byte 36 Table 2-8 Bit-Manipulation Instructions (cont) Instruction BIXOR Size* B Function C [( BLD BILD B BST BIST Note: * Size: Operand size B: Byte Notes on Bit Manipulation Instructions: BSET, BCLR, BNOT, BST, and BIST are read-modifywrite instructions. They read a byte of data, modify one bit in the byte, then write the byte back. Care is required when these instructions are applied to registers with write-only bits and to the I/O port registers. Step 1 2 3 Read Modify Write Description Read one data byte at the specified address Modify one bit in the data byte Write the modified data byte back to the specified address Example 1: BCLR is executed to clear bit 0 in the port 1 data direction register (P1DDR) under the following conditions. P17: Input pin, low P16: Input pin, high P15 - P10: Output pins, low The intended purpose of this BCLR instruction is to switch P10 from output to input. 37 Before Execution of BCLR Instruction P17 Input/output Pin state DDR DR Input Low 0 1 P16 Input High 0 0 P15 Output Low 1 0 P14 Output Low 1 0 P13 Output Low 1 0 P12 Output Low 1 0 P11 Output Low 1 0 P10 Output Low 1 0 Execution of BCLR Instruction BCLR #0, @P1DDR ;clear bit 0 in data direction register After Execution of BCLR Instruction P17 Input/output Pin state DDR DR Output Low 1 1 P16 Output High 1 0 P15 Output Low 1 0 P14 Output Low 1 0 P13 Output Low 1 0 P12 Output Low 1 0 P11 Output Low 1 0 P10 Input High 0 0 Explanation: To execute the BCLR instruction, the CPU begins by reading P1DDR. Since P1DDR is a write-only register, it is read as H'FF, even though its true value is H'3F. Next the CPU clears bit 0 of the read data, changing the value to H'FE. Finally, the CPU writes this value (H'FE) back to P1DDR to complete the BCLR instruction. As a result, P10DDR is cleared to 0, making P10 an input pin. In addition, P17DDR and P16DDR are set to 1, making P17 and P16 output pins. 38 BSET, BCLR, BNOT, BTST 15 8 7 0 op 15 8 7 IMM rn 0 Operand: register direct (Rn) Bit no.: immediate (#xx:3) Operand: register direct (Rn) Bit no.: register direct (Rm) 0 op 15 8 7 rm rn op op 15 8 7 rn IMM 0 0 0 0 0 0 0 Operand: register indirect (@Rn) 0 Bit no.: 0 immediate (#xx:3) op op 15 8 7 rn rm 0 0 0 0 0 0 0 Operand: register indirect (@Rn) 0 Bit no.: 0 register direct (Rm) op op 15 8 7 abs IMM 0 0 0 Operand: absolute (@aa:8) 0 Bit no.: 0 immediate (#xx:3) op op rm abs 0 0 0 Operand: absolute (@aa:8) 0 Bit no.: register direct (Rm) BAND, BOR, BXOR, BLD, BST 15 8 7 0 op 15 8 7 IMM rn 0 Operand: register direct (Rn) Bit no.: immediate (#xx:3) op op 15 8 7 rn IMM 0 0 0 0 0 0 0 Operand: register indirect (@Rn) 0 Bit no.: 0 immediate (#xx:3) op op IMM abs 0 0 0 Operand: absolute (@aa:8) 0 Bit no.: immediate (#xx:3) Legend op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2-7 Bit Manipulation Instruction Codes 39 2.5.6 Branching Instructions Table 2-9 describes the branching instructions. Figure 2-8 shows their object code formats. Table 2-9 Branching Instructions Instruction Bcc Size -- Function Branches if condition cc is true. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE JMP JSR BSR RTS -- -- -- -- cc field 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Always (true) Never (false) High Low or same Carry clear (High or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1 Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified displacement from the current address. Returns from a subroutine. 40 15 8 7 0 op 15 cc 8 7 disp 0 Bcc op 15 8 7 rm 0 0 0 0 0 JMP (@Rm) op abs 15 8 7 0 JMP (@aa:16) op 15 8 7 abs 0 JMP (@@aa:8) op 15 8 7 disp 0 BSR op 15 8 7 rm 0 0 0 0 0 JSR (@Rm) op abs 15 8 7 0 JSR (@aa:16) op 15 8 7 abs 0 JSR (@@aa:8) op Legend op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address RTS Figure 2-8 Branching Instruction Codes 41 2.5.7 System Control Instructions Table 2-10 describes the system control instructions. Figure 2-9 shows their object code formats. Table 2-10 System Control Instructions Inst5ruction RTE SLEEP LDC Size -- -- B Function Returns from an exception-handling routine. Causes a transition to the power-down state. Rs CCR, #imm CCR Moves immediate data or general register contents to the condition code register. CCR Rd Copies the condition code register to a specified general register. CCR #imm CCR Logically ANDs the condition code register with immediate data. CCR #imm CCR Logically ORs the condition code register with immediate data. CCR #imm CCR Logically exclusive-ORs the condition code register with immediate data. PC + 2 PC Only increments the program counter. STC ANDC ORC XORC NOP B B B B -- Note: * Size: Operand size B: Byte 15 8 7 0 op 15 8 7 0 RTE, SLEEP, NOP op 15 8 7 rn 0 LDC, STC (Rn) op IMM ANDC, ORC, XORC, LDC (#xx:8) Legend op: Operation field rn: Register field IMM: Immediate data Figure 2-9 System Control Instruction Codes 42 2.5.8 Block Data Transfer Instruction Table 2-11 describes the EEPMOV instruction. Figure 2-10 shows its object code format. Table 2-11 Block Data Transfer Instruction/EEPROM Write Operation Instruction EEPMOV Size -- Function if R4L 0 then repeat until else next; Moves a data block according to parameters set in general registers R4L, R5, and R6. R4L: size of block (bytes) R5: starting source address R6: starting destination address Execution of the next instruction starts as soon as the block transfer is completed. @R5+ @R6+ R4L - 1 R4L R4L = 0 15 8 7 0 op op Legend op: Operation field Figure 2-10 Block Data Transfer Instruction/EEPROM Write Operation Code 43 Notes on EEPMOV Instruction 1. The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. R5 R6 R5 + R4L R6 + R4L 2. When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of the instruction. R5 R6 H'FFFF Not allowed R6 + R4L R5 + R4L 44 2.6 CPU States 2.6.1 Overview The CPU has three states: the program execution state, exception-handling state, and power-down state. The power-down state is further divided into three modes: sleep mode, software standby mode, and hardware standby mode. Figure 2-11 summarizes these states, and figure 2-12 shows a map of the state transitions. State Program execution state The CPU executes successive program instructions. Exception-handling state A transient state triggered by a reset or interrupt. The CPU executes a hardware sequence that includes loading the program counter from the vector table. Power-down state A state in which some or all of the chip functions are stopped to conserve power. Sleep mode Software standby mode Hardware standby mode Figure 2-11 Operating States 45 Exception handling request Exceptionhandling state Program execution state Exception handing Interrupt request SLEEP instruction with SSBY bit set SLEEP instruction Sleep mode RES = 1 NMI or IRQ0 to IRQ2 Software standby mode Reset state STBY = 1, RES = 0 Hardware standby mode Power-down state Notes: 1. A transition to the reset state occurs when RES goes low, except when the chip is in the hardware standby mode. 2. A transition from any state to the hardware standby mode occurs when STBY goes low. Figure 2-12 State Transitions 2.6.2 Program Execution State In this state the CPU executes program instructions. 2.6.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU is reset or interrupted and changes its normal processing flow. In interrupt exception handling, the CPU references the stack pointer (R7) and saves the program counter and condition code register on the stack. For further details see section 4, Exception Handling. 2.6.4 Power-Down State The power-down state includes three modes: sleep mode, software standby mode, and hardware standby mode. (1) Sleep Mode: Is entered when a SLEEP instruction is executed. The CPU halts, but CPU register contents remain unchanged and the on-chip supporting modules continue to function. 46 (2) Software Standby Mode: Is entered if the SLEEP instruction is executed while the SSBY (Software Standby) bit in the system control register (SYSCR) is set. The CPU and all on-chip supporting modules halt. The on-chip supporting modules are initialized, but the contents of the onchip RAM and CPU registers remain unchanged as long as a specified voltage is supplied. I/O port outputs also remain unchanged. (3) Hardware Standby Mode: Is entered when the input at the STBY pin goes low. All chip functions halt, including I/O port output. The on-chip supporting modules are initialized, but onchip RAM contents are held. See section 15, Power-Down State, for further information. 2.7 Access Timing and Bus Cycle The CPU is driven by the system clock (o). The period from one rising edge of the system clock to the next is referred to as a "state." Memory access is performed in a two- or three-state bus cycle. On-chip memory, on-chip supporting modules, and external devices are accessed in different bus cycles as described below. 2.7.1 Access to On-Chip Memory (RAM and ROM) On-chip ROM and RAM are accessed in a cycle of two states designated T1 and T2. Either byte or word data can be accessed, via a 16-bit data bus. Figure 2-13 shows the on-chip memory access cycle. Figure 2-14 shows the associated pin states. 47 Bus cycle T1 state o T2 state Internal address bus Address Internal read signal Internal data bus (read) Read data Internal write signal Internal data bus (write) Write data Figure 2-13 On-Chip Memory Access Cycle Bus cycle T1 state o T2 state Address bus Address AS: High RD: High WR: High Data bus: high impedance state Figure 2-14 Pin States during On-Chip Memory Access Cycle 48 2.7.2 Access to On-Chip Register Field and External Devices The on-chip supporting module registers and external devices are accessed in a cycle consisting of three states: T1, T2, and T3. Only one byte of data can be accessed per cycle, via an 8-bit data bus. Access to word data or instruction codes requires two consecutive cycles (six states). Figure 2-15 shows the access cycle for the on-chip register field. Figure 2-16 shows the associated pin states. Figures 2-17 (a) and (b) show the read and write access timing for external devices. Bus cycle T1 state o Internal address bus Internal read signal Internal data bus (read) Internal write signal Internal data bus (write) T2 state T3 state Address Read data Write data Figure 2-15 On-Chip Register Field Access Cycle 49 Bus cycle T1 state o T2 state T3 state Address bus Address AS: High RD: High WR: High Data bus: high impedance state Figure 2-16 Pin States during On-Chip Register Field Access Cycle Read cycle T1 state o T2 state T3 state Address bus Address AS RD WR: High Data bus Read data Figure 2-17 (a) External Device Access Timing (Read) 50 Write cycle T1 state o T2 state T3 state Address bus Address AS RD: High WR Data bus Write data Figure 2-17 (b) External Device Access Timing (Write) 51 Section 3 MCU Operating Modes and Address Space 3.1 Overview 3.1.1 Mode Selection The H8/3297 Series operates in three modes numbered 1, 2, and 3. The mode is selected by the inputs at the mode pins (MD1 and MD0). See table 3-1. Table 3-1 Operating Modes Mode Mode 0 Mode 1 Mode 2 Mode 3 MD1 Low Low High High MD0 Low High Low High Address space -- Expanded Expanded Single-chip On-chip ROM -- Disabled Enabled Enabled On-chip RAM -- Enabled* Enabled* Enabled Note: * If the RAME bit in the system control register (SYSCR) is cleared to 0, off-chip memory can be accessed instead. Modes 1 and 2 are expanded modes that permit access to off-chip memory and peripheral devices. The maximum address space supported by these externally expanded modes is 64 kbytes. In mode 3 (single-chip mode), only on-chip ROM and RAM and the on-chip register field are used. All ports are available for general-purpose input and output. Mode 0 is inoperative in the H8/3297 Series. Avoid setting the mode pins to mode 0. 53 3.1.2 Mode and System Control Registers Table 3-2 lists the registers related to the chip's operating mode: the system control register (SYSCR) and mode control register (MDCR). The mode control register indicates the inputs to the mode pins MD1 and MD0. Table 3-2 Mode and System Control Registers Name System control register Mode control register Abbreviation SYSCR MDCR Read/Write R/W R Address H'FFC4 H'FFC5 3.2 System Control Register (SYSCR) Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 XRST 1 R 2 NMIEG 0 R/W 1 -- 1 -- 0 RAME 1 R/W The system control register (SYSCR) is an 8-bit register that controls the operation of the chip. Bit 7--Software Standby (SSBY): Enables transition to the software standby mode. For details, see section 15, Power-Down State. On recovery from software standby mode by an external interrupt, the SSBY bit remains set to 1. It can be cleared by writing 0. Bit 7 SSBY 0 1 Description The SLEEP instruction causes a transition to sleep mode. The SLEEP instruction causes a transition to software standby mode. (Initial value) 54 Bits 6 to 4--Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling time when the chip recovers from the software standby mode by an external interrupt. During the selected time the CPU and on-chip supporting modules continue to stand by. These bits should be set according to the clock frequency so that the settling time is at least 8 ms. For specific settings, see section 15.3.3, Clock Settling Time for Exit from Software Standby Mode. Bit 6 STS2 0 0 0 0 1 1 Bit 5 STS1 0 0 1 1 0 1 Bit 4 STS0 0 1 0 1 -- -- Description Settling time = 8,192 states Settling time = 16,384 states Settling time = 32,768 states Settling time = 65,536 states Settling time = 131,072 states Disabled (Initial value) Bit 3--External Reset (XRST): Indicates the source of a reset. A reset can be generated by input of an external reset signal, or by a watchdog timer overflow when the watchdog timer is used. XRST is a read-only bit. It is set to 1 by an external reset, and cleared to 0 by watchdog timer overflow. Bit 3 XRST 0 1 Description Reset was caused by watchdog timer overflow. Reset was caused by external input. (Initial value) Bit 2--NMI Edge (NMIEG): Selects the valid edge of the NMI input. Bit 2 NMIEG 0 1 Description An interrupt is requested on the falling edge of the NMI input. An interrupt is requested on the rising edge of the NMI input. (Initial value) 55 Bit 1--Reserved: This bit cannot be modified and is always read as 1. Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized by a reset, but is not initialized in the software standby mode. Bit 0 RAME 0 1 Description The on-chip RAM is disabled. The on-chip RAM is enabled. (Initial value) 3.3 Mode Control Register (MDCR) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 0 -- 3 -- 0 -- 2 -- 1 -- 1 MDS1 * R 0 MDS0 * R Note: * Initialized according to MD1 and MD0 inputs. The mode control register (MDCR) is an 8-bit register that indicates the operating mode of the chip. Bits 7 to 5--Reserved: These bits cannot be modified and are always read as 1. Bits 4 and 3--Reserved: These bits cannot be modified and are always read as 0. Bit 2--Reserved: This bit cannot be modified and is always read as 1. Bits 1 and 0--Mode Select 1 and 0 (MDS1 and MDS0): These bits indicate the values of the mode pins (MD1 and MD0), thereby indicating the current operating mode of the chip. MDS1 corresponds to MD1 and MDS0 to MD0. These bits can be read but not written. When the mode control register is read, the levels at the mode pins (MD1 and MD0) are latched in these bits. 56 3.4 Address Space Map in Each Operating Mode Figures 3-1 to 3-4 show memory maps of the H8/3297, H8/3296, H8/3294, and H8/3292 in modes 1, 2, and 3. Mode 1 Expanded Mode without On-Chip ROM H'0000 Vector table H'0049 H'004A H'0049 H'004A H'0000 Mode 2 Expanded Mode with On-Chip ROM H'0000 Vector table H'0049 H'004A Mode 3 Single-Chip Mode Vector table On-chip ROM, PROM 61,312 bytes On-chip ROM, PROM 63,360 bytes External address space H'EF7F H'EF80 External address apace H'F77F H'F780 On-chip RAM*, 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF H'F77F H'F780 On-chip RAM*, 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF H'FF7F H'FF88 H'FFFF H'FF7F H'F780 On-chip RAM, 2,048 bytes On-chip register field Note: * External memory can be accessed at these addresses when the RAME bit in the system control register (SYSCR) is cleared to 0. Figure 3-1 H8/3297 Address Space Map 57 Mode 1 Expanded Mode without On-Chip ROM H'0000 Vector table H'0049 H'004A H'0049 H'004A H'0000 Mode 2 Expanded Mode with On-Chip ROM H'0000 Vector table H'0049 H'004A Mode 3 Single-Chip Mode Vector table On-chip ROM 49,152 bytes On-chip ROM 49,152 bytes External address space H'BFFF H'C000 H'BFFF Reserved*1 H'EF7F H'EF80 External address space H'F77F H'F780 On-chip RAM *2 , 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF H'F77F H'F780 On-chip RAM *2 , 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF H'FF7F H'FF88 On-chip register field H'FFFF H'F77F H'F780 On-chip RAM 2,048 bytes Reserved*1 Notes: *1 Do not access reserved areas. *2 External memory can be accessed at these addresses when the RAME bit in the system control register (SYSCR) is cleared to 0. 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Figure 3-4 H8/3292 Address Space Map ?@ @?Y(?@eY0@4V?@?e@?e?Y0@?@?@@?e@?Y04V @@ @?5@?@?Y.O?K/V@?e@?e?5C??@?@@?e@Y.OK/f@?e@Y.O?K/V V?e@?e@?Y0@4V? @Y@@V@?5fL@@Be@?e?@e?@?@@?e@&f3?@@@?e@@fL3 @@C=@@?@J?e?@U@@@@? @?W??L@??K)Be J?e @@e@@?1N?eH@@Ce@?e?1B??@?@@Be@'V??H7?eX6@@@@/I?M?@ @7e1@?X/I?M.T)Be@? @X/IM.W?g?K/I?M.W ?K .W @7e1@?X/I?M.T)Be@?e?X6@@@?&T6@@@X/IM.W?g@@N?eH7 &WeX)eX6@2W?X6@@@?h?@f@?X62WehX6@2W? @? @?e'Ve@??@?Y(?e@@@4R0@@4IM0@4V?@?Y(?@e?@@@4R0@@4R0@@4R(?e@?@@4IM0@@@?/IM0@@@@@? @? @?e@3e@?H@R(@Ne@@?X@@e=@@C?=3?@?5@?@e?@e=@W??X@@e=@@?e@?@?U@@Ce@?L@&Of@? @?e@@e@?5T@&T3f@@@@e?@@?e@?@Y@@V@e?@e?@@@@@@@e?@@?e@?@@2W@?e@??@g@? 1Be@@*?@?@?@J?@e1V?YW@@@2OK6@2W?@@e@@e?@@@2OK6@2W@e<@@Be@?1V?8@Be@?H@'V?@@@@? X6@@@@N?@?@?@??@eX6@2@@e<@@B?<7?@@C=@@e?@e<@@V?Y@@@@2OK6@@@?X6@2T6@@@?.OK/f@? @@*? W@@@2OK6@2W?@@e@@e?@@@2OK6@2W@ @? X6@@@&W?@?@?@??@eX6@2?@eh@7e1@e?@h?@@@2OK6@@@?X6@2T6@@@?.OK/f@? &We@?fh?@eh&WeX)e?@h?@ @@@@@? @@?Y7?fX@@??=@@C?=3?@?5@?@? @@@??@@@4R0@@4IM0@4V?@?Y(?@? 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X6@2W?g@?h?&W??X)? 60 ?@ ?@ @ @?Y(?@eY0@4V?@?e@?e?Y0@@@?@@?e@?Y04Vf@?e@Y.O?K/V ?5@?@?Y.O?K/V@?e@?e?5C??@?@@?e@Y.OK/V?e@?e@?Y0@4V? @Y@@V@?5J?eL@@Be@?e?@e?@?@@?e@&W??L3?@@@?e@@J?e?@ @@C=@@?@f?@U@@@@?e?1B??@?@@Be@?f@??K)Be@@fL3 @@e@@?1N?eH@@Ce@? @'V??H7?eX6@@?K/I?M.W @7e1@?X/I?M.T)Be@? @X/IM.W?g?K/I?M.W @7e1@?X/I?M.T)B@@@?e?X6@@@?&T6@@@X/IM.W?g@@N?eH7 &WeX)eX6@2W?X6e@?h?@f@?X62WehX6@2W? @? ?/V?@@4V?Y0@4R(?e'Ve@??@?Y(?e@@@4R0@@4IM0@4V?@?Y(?@e?@@@4R0@@4R0@@4R(?e@?@@4IM0@@@?/IM0@@@@@? @? ?L@?@??@?@e?@@?e@@e@?5T@&T3e@@@@@@e?@@?e@?@Y@@V@e?@e?@@@@@@@e?@@?e@?@@2W@?e@??@g@? 3?@?=3?5C?=@@?e@3e@?H@R(@Nf?X@@e=@@C?=3?@?5@?@e?@e=@W??X@@e=@@?e@?@?U@@Ce@?L@&Of@? ?H@?@??@?X6@2OK6@@@@N?@?@?@J?@e1V?Y@@@@<@@B?<7?@@C=@@e?@@@<@@V?Y@@@@2OK6@@@?X6@2T6@@@?.OK/f@? @? ?)@@ @@*?@?@?@??@eX6@2W@@@2OK6@2W?@@e@@e?@@@2OK6@2W@ @? ?)@@@??@?1B?<@@Be@@*?@?@?@??@eX6@2W@e2OK6@2W?@@e@@e?@e2OK6@2W@e<@@Be@?1V?8@Be@?H@'V?@@@@? ?X)O@??@?X6@2OK6@@@&W?@?fh?@eh@7e1@e?@h?@@@2OK6@@@?X6@2T6@@@?.OK/f@? &We ?@eh&WeX)e?@h?@ @@@@ ?@f@@@4R0@@4IM0?=V?@?Y(?@ @4 ?@g?X@@e=@@Ce3?@?5@?@ ?@N?e@@@@@@e<@@B?<7?@@C=@@ @@ ?@@? @?@Y@@V@ ?@@?e1V?YW@e2OK6@2W?@@e@@ ?@J?eX6@2?@eh@7e1@ @@ ?@h?@eh&WeX) Section 4 Exception Handling 4.1 Overview The H8/3297 Series recognizes two kinds of exceptions: interrupts and the reset. Table 4-1 indicates their priority and the timing of their hardware exception-handling sequence. Table 4-1 Hardware Exception-Handling Sequences and Priority Priority High Type of Exception Reset Interrupt Detection Timing Synchronized with clock End of instruction execution* Timing of Exception-Handling Sequence The hardware exception-handling sequence begins as soon as RES changes from low to high. When an interrupt is requested, the hardware exception-handling sequence begins at the end of the current instruction, or at the end of the current hardware exception-handling sequence. Low Note: * Not detected after ANDC, ORC, XORC, and LDC instructions. 4.2 Reset 4.2.1 Overview A reset has the highest exception-handling priority. When the RES pin goes low, or when there is a watchdog timer reset (when the reset option is selected for watchdog timer overflow), all current processing stops and the chip enters the reset state. The internal state of the CPU and the registers of the on-chip supporting modules are initialized. The reset exception-handling sequence starts when RES returns from low to high, or at the end of a watchdog reset pulse. 4.2.2 Reset Sequence The reset state begins when RES goes low or a watchdog reset is generated. To ensure correct resetting, at power-on the RES pin should be held low for at least 20 ms. In a reset during operation, the RES pin should be held low for at least 10 system clock cycles. The watchdog reset pulse width is always 518 system clocks. For the pin states during a reset, see appendix D, Pin States. The following sequence is carried out when reset exception handling begins. (1) The internal state of the CPU and the registers of the on-chip supporting modules are initialized, and the I bit in the condition code register (CCR) is set to 1. (2) The CPU loads the program counter with the first word in the vector table (stored at addresses H'0000 and H'0001) and starts program execution. The RES pin should be held low when power is switched off, as well as when power is switched on. 61 Figure 4-1 indicates the timing of the reset sequence in modes 2 and 3. Figure 4-2 indicates the timing in mode 1. Vector fetch RES/watchdog timer reset (internal) o Internal address bus Internal read signal Internal write signal Internal data bus (16 bits) (1) Reset vector address (H'0000) (2) Starting address of program (3) First instruction of program (2) Internal Instruction processing prefetch (1) (2) (3) Figure 4-1 Reset Sequence (Mode 2 or 3, Program Stored in On-Chip ROM) 62 Vector fetch Internal processing Instruction prefetch RES/watchdog timer reset (internal) o (3) (5) (7) A15 to A0 (1) RD 63 (2) (4) WR D7 to D0 (8 bits) (6) (8) (1), (3) (2), (4) (5), (7) (6), (8) Reset vector address: (1) = H'0000, (3) = H'0001 Starting address of program (contents of reset vector): (2) = upper byte, (4) = lower byte Starting address of program: (5) = (2) (4), (7) = (2) (4) + 1 First instruction of program: (6) = first byte, (8) = second byte Figure 4-2 Reset Sequence (Mode 1) 4.2.3 Disabling of Interrupts after Reset After a reset, if an interrupt were to be accepted before initialization of the stack pointer (SP: R7), the program counter and condition code register might not be saved correctly, leading to a program crash. To prevent this, all interrupts, including NMI, are disabled immediately after a reset. The first program instruction is therefore always executed. This instruction should initialize the stack pointer (example: MOV.W #xx:16, SP). After reset exception handling, in order to initialize the contents of CCR, a CCR manipulation instruction can be executed before an instruction to initialize the stack pointer. Immediately after execution of a CCR manipulation instruction, all interrupts including NMI are disabled. Use the next instruction to initialize the stack pointer. 4.3 Interrupts 4.3.1 Overview The interrupt sources include four external sources (NMI, and IRQ0 to IRQ2), and 19 internal sources in the on-chip supporting modules. Table 4-2 lists the interrupt sources in priority order and gives their vector addresses. When two or more interrupts are requested, the interrupt with highest priority is served first. The features of these interrupts are: * NMI has the highest priority and is always accepted. All internal and external interrupts except NMI can be masked by the I bit in the CCR. When the I bit is set to 1, interrupts other than NMI are not accepted. IRQ0 to IRQ2 can be sensed on the falling edge of the input signal, or level-sensed. The type of sensing can be selected for each interrupt individually. NMI is edge-sensed, and either the rising or falling edge can be selected. All interrupts are individually vectored. The software interrupt-handling routine does not have to determine what type of interrupt has occurred. The watchdog timer can generate either an NMI or overflow interrupt, depending on the needs of the application. For details, see section 10, Watchdog Timer. * * * 64 Table 4-2 Interrupts Interrupt source NMI IRQ0 IRQ1 IRQ2 Reserved No. 3 4 5 6 7 8 9 10 11 ICIA (Input capture A) ICIB (Input capture B) ICIC (Input capture C) ICID (Input capture D) OCIA (Output compare A) OCIB (Output compare B) FOVI (Overflow) CMI0A (Compare-match A) CMI0B (Compare-match B) OVI0 (Overflow) CMI1A (Compare-match A) CMI1B (Compare-match B) OVI1 (Overflow) 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 ERI (Receive error) RXI (Receive end) TXI (TDR empty) TEI (TSR empty) 27 28 29 30 31 32 33 34 ADI (Conversion end) WOVF (WDT overflow) 35 36 Vector Table Address Priority H'0006 to H'0007 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 H'002A to H'002B H'002C to H'002D H'002E to H'002F H'0030 to H'0031 H'0032 to H'0033 H'0034 to H'0035 H'0036 to H'0037 H'0038 to H'0039 H'003A to H'003B H'003C to H'003D H'003E to H'003F H'0040 to H'0041 H'0042 to H'0043 H'0044 to H'0045 H'0046 to H'0047 H'0048 to H'0049 Low High 16-bit freerunning timer 8-bit timer 0 8-bit timer 1 Reserved Serial communication interface Reserved A/D converter Watchdog timer Notes: 1. H'0000 and H'0001 contain the reset vector. 2. H'0002 to H'0005 are reserved in the H8/3297 Series and are not available to the user. 65 4.3.2 Interrupt-Related Registers The interrupt-related registers are the system control register (SYSCR), IRQ sense control register (ISCR), and IRQ enable register (IER). Table 4-3 Registers Read by Interrupt Controller Name System control register IRQ sense control register IRQ enable register Abbreviation SYSCR ISCR IER Read/write R/W R/W R/W Address H'FFC4 H'FFC6 H'FFC7 System Control Register (SYSCR) Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 XRST 1 R 2 NMIEG 0 R/W 1 -- 1 -- 0 RAME 1 R/W The valid edge on the NMI line is controlled by bit 2 (NMIEG) in the system control register. Bit 2--NMI Edge (NMIEG): Determines whether a nonmaskable interrupt is generated on the falling or rising edge of the NMI input signal. Bit 2 NMIEG 0 1 Description An interrupt is generated on the falling edge of NMI. An interrupt is generated on the rising edge of NMI. (Initial state) See section 3.2, System Control Register, for information on the other SYSCR bits. IRQ Sense Control Register (ISCR)--H'FFC6 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 0 R/W 1 0 R/W 0 0 R/W IRQ2SC IRQ1SC IRQ0SC Bits 7 to 3--Reserved: These bits cannot be modified and are always read as 1 66 Bits 2 to 0--IRQ2 to IRQ0 Sense Control (IRQ2SC to IRQ0SC): These bits determine whether IRQ2 to IRQ0 are level-sensed or sensed on the falling edge. Bits 2 to 0 IRQ2SC to IRQ0SC 0 1 Description An interrupt is generated when IRQ2 to IRQ0 inputs are low. (Initial state) An interrupt is generated by the falling edge of the IRQ2 to IRQ0 inputs. IRQ Enable Register (IER) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W Bits 7 to 3--Reserved: These bits cannot be modified and are always read as 1 Bits 2 to 0--IRQ2 to IRQ0 Enable (IRQ2E to IRQ0E): These bits enable or disable the IRQ2 to IRQ0 interrupts individually. Bits 2 to 0 IRQ2E to IRQ0E 0 1 IRQ2 to IRQ0 interrupt requests are disabled. IRQ2 to IRQ0 interrupt requests are enabled. Description (Initial state) When edge sensing is selected (by setting bits IRQ2SC to IRQ0SC to 1), it is possible for an interrupt-handling routine to be executed even though the corresponding enable bit (IRQ2E to IRQ0E) is cleared to 0 and the interrupt is disabled. If an interrupt is requested while the enable bit (IRQ2E to IRQ0E) is set to 1, the request will be held pending until served. If the enable bit is cleared to 0 while the request is still pending, the request will remain pending, although new requests will not be recognized. If the interrupt mask bit (I) in the CCR is cleared to 0, the interrupthandling routine can be executed even though the enable bit is now 0. If execution of interrupt-handling routines under these conditions is not desired, it can be avoided by using the following procedure to disable and clear interrupt requests. 1. Set the I bit to 1 in the CCR, masking interrupts. Note that the I bit is set to 1 automatically when execution jumps to an interrupt vector. Clear the desired bits from IRQ2E to IRQ0E to 0 to disable new interrupt requests. Clear the corresponding IRQ2SC to IRQ0SC bits to 0, then set them to 1 again. Pending IRQn interrupt requests are cleared when I = 1 in the CCR, IRQnSC = 0, and IRQnE = 0. 2. 3. 67 4.3.3 External Interrupts The four external interrupts are NMI and IRQ2 to IRQ0. These four interrupts can be used to recover from software standby mode. (1) NMI: A nonmaskable interrupt is generated on the rising or falling edge of the NMI input signal regardless of whether the I (interrupt mask) bit is set in the CCR. The valid edge is selected by the NMIEG bit in the system control register. The NMI vector number is 3. In the NMI hardware exception-handling sequence the I bit in the CCR is set to 1. (2) IRQ2 to IRQ0: These interrupt signals are level-sensed or sensed on the falling edge of the input, as selected by ISCR bits IRQ2SC to IRQ0SC. These interrupts can be masked collectively by the I bit in the CCR, and can be enabled and disabled individually by setting and clearing bits IRQ2E to IRQ0E in the IRQ enable register. When one of these interrupts is accepted, the I bit is set to 1. IRQ2 to IRQ0 have interrupt vector numbers 4 to 6. They are prioritized in order from IRQ2 (low) to IRQ0 (high). For details, see table 4-2. Interrupts IRQ2 to IRQ0 do not depend on whether pins IRQ2 to IRQ0 are input or output pins. When using external interrupts IRQ2 to IRQ0, clear the corresponding DDR bits to 0 to set these pins to the input state, and do not use these pins as input or output pins for the timers, serial communication interface, or A/D converter. 4.3.4 Internal Interrupts Nineteen internal interrupts can be requested by the on-chip supporting modules. Each interrupt source has its own vector number, so the interrupt-handling routine does not have to determine which interrupt has occurred. All internal interrupts are masked when the I bit in the CCR is set to 1. When one of these interrupts is accepted, the I bit is set to 1 to mask further interrupts (except NMI). The vector numbers are 12 to 36. For the priority order, see table 4-2. 68 4.3.5 Interrupt Handling Interrupts are controlled by an interrupt controller that arbitrates between simultaneous interrupt requests, commands the CPU to start the hardware interrupt exception-handling sequence, and furnishes the necessary vector number. Figure 4-3 shows a block diagram of the interrupt controller. NMI interrupt IRQ0 flag IRQ0E * IRQ0 interrupt Priority decision Interrupt controller CPU Interrupt request Vector number OVF TME WOVF interrupt I (CCR) Note: * For edge-sensed interrupts, these AND gates change to the circuit shown below. IRQ0 edge IRQ0E IRQ0 flag S Q IRQ0 interrupt Figure 4-3 Block Diagram of Interrupt Controller The IRQ interrupts and interrupts from the on-chip supporting modules (except for reset selected for a watchdog timer overflow) all have corresponding enable bits. When the enable bit is cleared to 0, the interrupt signal is not sent to the interrupt controller, so the interrupt is ignored. These interrupts can also all be masked by setting the CPU's interrupt mask bit (I) to 1. Accordingly, these interrupts are accepted only when their enable bit is set to 1 and the I bit is cleared to 0. The nonmaskable interrupt (NMI) is always accepted, except in the reset state and hardware standby mode. 69 When an NMI or another enabled interrupt is requested, the interrupt controller transfers the interrupt request to the CPU and indicates the corresponding vector number. (When two or more interrupts are requested, the interrupt controller selects the vector number of the interrupt with the highest priority.) When notified of an interrupt request, at the end of the current instruction or current hardware exception-handling sequence, the CPU starts the hardware exception-handling sequence for the interrupt and latches the vector number. Figure 4-4 is a flowchart of the interrupt (and reset) operations. Figure 4-6 shows the interrupt timing sequence for the case in which the software interrupt-handling routine is in on-chip ROM and the stack is in on-chip RAM. (1) An interrupt request is sent to the interrupt controller when an NMI interrupt occurs, and when an interrupt occurs on an IRQ input line or in an on-chip supporting module provided the enable bit of that interrupt is set to 1. (2) The interrupt controller checks the I bit in CCR and accepts the interrupt request if the I bit is cleared to 0. If the I bit is set to 1 only NMI requests are accepted; other interrupt requests remain pending. (3) Among all accepted interrupt requests, the interrupt controller selects the request with the highest priority and passes it to the CPU. Other interrupt requests remain pending. (4) When it receives the interrupt request, the CPU waits until completion of the current instruction or hardware exception-handling sequence, then starts the hardware exception-handling sequence for the interrupt and latches the interrupt vector number. (5) In the hardware exception-handling sequence, the CPU first pushes the PC and CCR onto the stack. See figure 4-5. The stacked PC indicates the address of the first instruction that will be executed on return from the software interrupt-handling routine. (6) Next the I bit in CCR is set to 1, masking all further interrupts except NMI. (7) The vector address corresponding to the vector number is generated, the vector table entry at this vector address is loaded into the program counter, and execution branches to the software interrupt-handling routine at the address indicated by that entry. 70 Program execution Interrupt requested? Yes Yes NMI? No No No I = 0? Yes IRQ0? Yes IRQ1? Yes WOVF? Yes No No Pending Latch vector no. Save PC Reset Save CCR I1 Read vector address Branch to software interrupt-handling routine Figure 4-4 Hardware Interrupt-Handling Sequence 71 SP - 4 SP - 3 SP - 2 SP - 1 SP (R7) Stack area SP(R7) SP + 1 SP + 2 SP + 3 SP + 4 CCR CCR* PC (upper byte) PC (lower byte) Even address Before interrupt is accepted Pushed onto stack After interrupt is accepted PC: Program counter CCR: Condition code register SP: Stack pointer Notes: 1. The PC contains the address of the first instruction executed after return. 2. Registers must be saved and restored by word access at an even address. * Ignored on return. Figure 4-5 Usage of Stack in Interrupt Handling The CCR is comprised of one byte, but when it is saved to the stack, it is treated as one word of data. During interrupt processing, two identical bytes of CCR data are saved to the stack to create one word of data. When the RTE instruction is executed to restore the value from the stack, the byte located at the even address is loaded into CCR, and the byte located at the odd address is ignored. 72 Interrupt accepted Interrupt priority decision. Wait for Instruction Internal end of instruction. prefetch processing Interrupt request signal Vector fetch Stack Instruction prefetch (first instruction of Internal interrupt-handling process- routine) ing o Internal address bus (1) (3) (5) (6) (8) (9) Internal read signal Internal write signal Internal 16-bit data bus (2) (4) (1) (7) (9) (10) (1) Instruction prefetch address (Pushed on stack. Instruction is executed on return from interrupt-handling routine.) (2) (4) Instruction code (Not executed) (3) Instruction prefetch address (Not executed) (5) SP-2 (6) SP-4 (7) CCR (8) Address of vector table entry (9) Vector table entry (address of first instruction of interrupt-handling routine) (10) First instruction of interrupt-handling routine Figure 4-6 Timing of Interrupt Sequence 73 4.3.6 Interrupt Response Time Table 4-4 indicates the number of states that elapse from an interrupt request signal until the first instruction of the software interrupt-handling routine is executed. Since on-chip memory is accessed 16 bits at a time, very fast interrupt service can be obtained by placing interrupt-handling routines in on-chip ROM and the stack in on-chip RAM. Table 4-4 Number of States before Interrupt Service Number of States No. 1 2 3 4 5 6 Reason for Wait Interrupt priority decision Wait for completion of current instruction*1 Save PC and CCR Fetch vector Fetch instruction Internal processing Total On-Chip Memory 2*3 1 to 13 4 2 4 4 17 to 29 External Memory 2*3 5 to 17*2 12*2 6*2 12*2 4 41 to 53 *2 Notes: 1. These values do not apply if the current instruction is EEPMOV. 2. If wait states are inserted in external memory access, add the number of wait states. 3. 1 for internal interrupts. 74 4.3.7 Precaution Note that the following type of contention can occur in interrupt handling. When software clears the enable bit of an interrupt to 0 to disable the interrupt, the interrupt becomes disabled after execution of the clearing instruction. If an enable bit is cleared by a BCLR or MOV instruction, for example, and the interrupt is requested during execution of that instruction, at the instant when the instruction ends the interrupt is still enabled, so after execution of the instruction, the hardware exception-handling sequence is executed for the interrupt. If a higherpriority interrupt is requested at the same time, however, the hardware exception-handling sequence is executed for the higher-priority interrupt and the interrupt that was disabled is ignored. Similar considerations apply when an interrupt request flag is cleared to 0. Figure 4-7 shows an example in which the OCIAE bit is cleared to 0. CPU write cycle to TIER o Internal address bus TIER address OCIA interrupt handling Internal write signal OCIAE OCFA OCIA interrupt signal Figure 4-7 Contention between Interrupt and Disabling Instruction The above contention does not occur if the enable bit or flag is cleared to 0 while the interrupt mask bit (I) is set to 1. 75 4.4 Note on Stack Handling In word access, the least significant bit of the address is always assumed to be 0. The stack is always accessed by word access. Care should be taken to keep an even value in the stack pointer (general register R7). Use the PUSH and POP (or MOV.W Rn, @-SP and MOV.W @SP+, Rn) instructions to push and pop registers on the stack. Setting the stack pointer to an odd value can cause programs to crash. Figure 4-8 shows an example of damage caused when the stack pointer contains an odd address. PCH SP PCL SP R1L PCL H'FECC H'FECD SP H'FECF BSR instruction MOV.B R1L, @-R7 H'FECF set in SP PC is improperly stored beyond top of stack PCH is lost PCH: PCL: R1L: SP: Upper byte of program counter Lower byte of program counter General register Stack pointer Figure 4-8 Example of Damage Caused by Setting an Odd Address in R7 76 Section 5 Wait-State Controller 5.1 Overview The H8/3297 Series has an on-chip wait-state controller that enables insertion of wait states into bus cycles for interfacing to low-speed external devices. 5.1.1 Features Features of the wait-state controller are listed below. * * Three selectable wait modes: programmable wait mode, pin auto-wait mode, and pin wait mode Automatic insertion of zero to three wait states 5.1.2 Block Diagram Figure 5-1 shows a block diagram of the wait-state controller. Internal data bus WAIT Wait-state controller (WSC) WSCR Wait request signal Legend WSCR: Wait-state control register Figure 5-1 Block Diagram of Wait-State Controller 77 5.1.3 Input/Output Pins Table 5-1 summarizes the wait-state controller's input pin. Table 5-1 Wait-State Controller Pins Name Wait Abbreviation WAIT I/O Input Function Wait request signal for access to external addresses 5.1.4 Register Configuration Table 5-2 summarizes the wait-state controller's register. Table 5-2 Register Configuration Address H'FFC2 Name Wait-state control register Abbreviation WSCR R/W R/W Initial Value H'08 5.2 Register Description 5.2.1 Wait-State Control Register (WSCR) WSCR is an 8-bit readable/writable register that selects the wait mode for the wait-state controller (WSC) and specifies the number of wait states. It also controls frequency division of the clock signals supplied to the supporting modules. Bit Initial value Read/Write 7 -- 0 R/W 6 -- 0 R/W 5 CKDBL 0 R/W 4 -- 0 R/W 3 WMS1 1 R/W 2 WMS0 0 R/W 1 WC1 0 R/W 0 WC0 0 R/W WSCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. 78 Bits 7 and 6--Reserved Bit 5--Clock Double (CKDBL): Controls frequency division of clock signals supplied to supporting modules. For details, see section 6, Clock Pulse Generator. Bit 4--Reserved: This bit is reserved, but it can be written and read. Its initial value is 0. Bits 3 and 2--Wait Mode Select 1 and 0 (WMS1/0): These bits select the wait mode. Bit 3 WMS1 0 Bit 2 WMS0 0 1 1 0 1 Description Programmable wait mode No wait states inserted by wait-state controller Pin wait mode Pin auto-wait mode (Initial value) Bits 1 and 0--Wait Count 1 and 0 (WC1/0): These bits select the number of wait states inserted in access to external address areas. Bit 1 WC1 0 Bit 0 WC0 0 1 1 0 1 Description No wait states inserted by wait-state controller 1 state inserted 2 states inserted 3 states inserted (Initial value) 79 5.3 Wait Modes Analog power supply: Analog power supply pin for the A/D converter. If the A/D converter is not used, connect AVCC to the system power supply (VCC). Figure 5-2 shows the timing when the wait count is 1 (WC = 0, WC0 = 1). T1 T2 TW T3 o Address bus External address AS RD Read access Data bus Read data WR Write access Data bus Write data Figure 5-2 Programmable Wait Mode 80 Pin Wait Mode: In all accesses to external addresses, the number of wait states (TW) selected by bits WC1 and WC0 are inserted. If the WAIT pin is low at the fall of the system clock (o) in the last of these wait states, an additional wait state is inserted. If the WAIT pin remains low, wait states continue to be inserted until the WAIT signal goes high. Pin wait mode is useful for inserting four or more wait states, or for inserting different numbers of wait states for different external devices. Figure 5-3 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1) and one additional wait state is inserted by WAIT input. Inserted by wait count T1 o T2 TW Inserted by WAIT signal TW T3 * * WAIT pin Address bus External address AS Read access RD Read data Data bus WR Write access Data bus Write data Note: * Arrows indicate time of sampling of the WAIT pin. Figure 5-3 Pin Wait Mode 81 Pin Auto-Wait Mode: If the WAIT pin is low, the number of wait states (TW) selected by bits WC1 and WC0 are inserted. In pin auto-wait mode, if the WAIT pin is low at the fall of the system clock (o) in the T2 state, the number of wait states (TW) selected by bits WC1 and WC0 are inserted. No additional wait states are inserted even if the WAIT pin remains low. Pin auto-wait mode can be used for an easy interface to low-speed memory, simply by routing the chip select signal to the WAIT pin. Figure 5-4 shows the timing when the wait count is 1. T1 T2 T3 T4 T 2 T W T 3 o * * WAIT Address bus External address External address AS RD Read access Data bus Read data Read data WR Write access Data bus Write data Write data Note: * Arrows indicate time of sampling of the WAIT pin. Figure 5-4 Pin Auto-Wait Mode 82 Section 6 Clock Pulse Generator 6.1 Overview The H8/3297 Series has a built-in clock pulse generator (CPG) consisting of an oscillator circuit, a duty adjustment circuit, and a divider and a prescaler that generates clock signals for the on-chip supporting modules. 6.1.1 Block Diagram Figure 6-1 shows a block diagram of the clock pulse generator. XTAL EXTAL Oscillator circuit Duty adjustment circuit o (system clock) oP (for supporting modules) Prescaler Frequency divider (1/2) CKDBL oP/2 to oP/4096 Figure 6-1 Block Diagram of Clock Pulse Generator Input an external clock signal to the EXTAL pin, or connect a crystal resonator to the XTAL and EXTAL pins. The system clock frequency (o) will be the same as the input frequency. This same system clock frequency (oP) can be supplied to timers and other supporting modules, or it can be divided by two. The selection is made by software, by controlling the CKDBL bit. 83 6.1.2 Wait-State Control Register (WSCR) WSCR is an 8-bit readable/writable register that controls frequency division of the clock signals supplied to the supporting modules. It also controls wait-state insertion. WSCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit Initial value Read/Write 7 -- 0 R/W 6 -- 0 R/W 5 CKDBL 0 R/W 4 -- 0 R/W 3 WMS1 1 R/W 2 WMS0 0 R/W 1 WC1 0 R/W 0 WC0 0 R/W Bits 7 and 6--Reserved Bit 5--Clock Double (CKDBL): Controls the frequency division of clock signals supplied to supporting modules. Bit 5 CKDBL 0 1 Description The undivided system clock (o) is supplied as the clock (oP) for supporting modules. (Initial value) The system clock (o) is divided by two and supplied as the clock (oP) for supporting modules. Bit 4--Reserved: This bit is reserved, but it can be written and read. Its initial value is 0. Bits 3 and 2--Wait Mode Select 1 and 0 (WMS1/0) Bits 1 and 0--Wait Count 1 and 0 (WC1/0) These bits control wait-state insertion. For details, see section 5, Wait-State Controller. 84 6.2 Oscillator Circuit If an external crystal is connected across the EXTAL and XTAL pins, the on-chip oscillator circuit generates a system clock signal. Alternatively, an external clock signal can be applied to the EXTAL pin. (1) Connecting an External Crystal Circuit Configuration: An external crystal can be connected as in the example in figure 6-2. Table 6-1 indicates the appropriate damping resistance Rd. An AT-cut parallel resonance crystal should be used. C L1 EXTAL XTAL Rd C L2 C L1 = C L2 = 10 pF to 22 pF Figure 6-2 Connection of Crystal Oscillator (Example) Table 6-1 Damping Resistance Frequency (MHz) Rd max () 2 1k 4 500 8 200 12 0 16 0 85 Crystal Oscillator: Figure 6-3 shows an equivalent circuit of the crystal resonator. The crystal resonator should have the characteristics listed in table 6-2. CL L XTAL Rs EXTAL CO AT-cut parallel resonating crystal Figure 6-3 Equivalent Circuit of External Crystal Table 6-2 External Crystal Parameters Frequency (MHz) Rs max () C0 (pF) 2 500 4 120 8 80 7 pF max 12 60 16 50 Use a crystal with the same frequency as the desired system clock frequency (o). 86 Note on Board Design: When an external crystal is connected, other signal lines should be kept away from the crystal circuit to prevent induction from interfering with correct oscillation. See figure 6-4. The crystal and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins. Not allowed Signal A Signal B C L2 XTAL EXTAL C L1 Figure 6-4 Notes on Board Design around External Crystal 87 (2) Input of External Clock Signal Circuit Configuration: An external clock signal can be input as shown in the examples in figure 6-5. In example (b) in figure 6-5, the external clock signal should be kept high during standby. If the XTAL pin is left open, make sure the stray capacitance does not exceed 10 pF. EXTAL External clock input XTAL Open (a) Connections with XTAL pin left open EXTAL 74HC04 XTAL External clock input (b) Connections with inverted clock input at XTAL pin Figure 6-5 External Clock Input (Example) 88 External Clock Input The external clock signal should have the same frequency as the desired system clock (o). Clock timing parameters are given in table 6-3 and figure 6-6. Table 6-3 Clock Timing VCC = 2.7 to 5.5 V Item Symbol Min 40 Max -- Low pulse tEXL width of external clock input High pulse tEXH width of external clock input External clock rise time External clock fall time Clock pulse width low Clock pulse width high tEXr tEXf tCL tCH VCC = 5.0 V 10% Min 20 Max -- Unit Test Conditions ns Figure 6-6 40 -- 20 -- ns -- -- 0.3 0.4 0.3 0.4 10 10 0.7 0.6 0.7 0.6 -- -- 0.3 0.4 0.3 0.4 5 5 0.7 0.6 0.7 0.6 ns ns tcyc tcyc tcyc tcyc o 5 MHz Figure 16-4 o < 5 MHz o 5 MHz o < 5 MHz tEXH tEXL EXTAL VCC x 0.5 tEXr tEXt Figure 6-6 External Clock Input Timing 89 Table 6.4 shows the external clock output settling delay time, and figure 6.7 shows the external clock output settling delay timing. The oscillator and duty adjustment circuit have the function of adjusting the waveform of the external clock input at the EXTAL pin. When the specified clock signal is input at the EXTAL pin, internal clock signal output settles after the elapse of the external clock output settling delay time (tDEXT). As the clock signal output remains unsettled during the tDEXT period, the reset signal should be driven low to retain the reset state. Table 6-4 External Clock Output Settling Delay Time Conditions: VCC = 2.7 V to 5.5 V, AVCC 2.7 V to 5.5 V, VSS = AVSS = 0 V Item External clock output settling delay time Symbol tDEXT* Min 500 Max - Unit s Note Figure 6-7 Note: * tDEXT includes an RES pulse width (tRESW) of 10 tcyc. 2.7V VCC VIH STBY EXTAL o (Internal or extenal) RES tDEXT* Note: * tDEXT includes an RES pulse width (tRESW) of 10 tcyc. Figure 6-7 External Clock Output Settling Delay Time 6.3 Duty Adjustment Circuit When the clock frequency is 5 MHz or above, the duty adjustment circuit adjusts the duty cycle of the signal from the oscillator circuit to generate the system clock (o). 6.4 Prescaler The clock for the on-chip supporting modules (oP) has either the same frequency as the system clock (o) or this frequency divided by two, depending on the CKDBL bit. The prescaler divides the frequency of oP to generate internal clock signals with frequencies from oP/2 to oP/4096. 90 Section 7 I/O Ports 7.1 Overview The H8/3297 Series has five 8-bit input/output ports, one 8-bit input port, and one 3-bit input/output port. Table 7-1 lists the functions of each port in each operating mode. As table 7-1 indicates, the port pins are multiplexed, and the pin functions differ depending on the operating mode. Each port has a data direction register (DDR) that selects input or output, and a data register (DR) that stores output data. If bit manipulation instructions will be executed on the port data direction registers, see "Notes on Bit Manipulation Instructions" in section 2.5.5, Bit Manipulation Instructions. Ports 1 to 4, and 6 can drive one TTL load and a 90-pF capacitive load. Port 5 can drive one TTL load and a 30-pF capacitive load. Ports 1 and 2 can drive LEDs (with 10-mA current sink). Ports 1 to 6 can drive a darlington pair. Ports 1 to 3 have built-in MOS pull-up transistors. For block diagrams of the ports, see appendix C, I/O Port Block Diagrams. 91 Table 7-1 Port Functions Expanded Modes Port Port 1 Description * 8-bit I/O port * Can drive LEDs * Built-in input pull-ups * 8-bit I/O port * Can drive LEDs * Built-in input pull-ups * 8-bit I/O port * Built-in input pull-ups Pins P17 to P10/A7 to A0 Mode 1 Lower address output (A7 to A0) Mode 2 Lower address output (A7 to A0) or general input Upper address output (A15 to A8) or general input Single-Chip Mode Mode 3 General input/output Port 2 P27 to P20/A15 to A8 Upper address output (A15 to A8) General input/output Port 3 P37 to P30/ D7 to D0/ Data bus (D7 to D0) General input/output Port 4 * 8-bit I/O port P47/WAIT Expanded data bus control input (WAIT)/ General General input/output input/output P46/o P45/AS P44/WR P43/RD P42/IRQ0 P41/IRQ1 P40/IRQ2/ADTRG Port 5 * 3-bit I/O port P52/SCK P51/RxD P50/TxD P67/TMO1 P66/FTOB/TMRI1 P65/FTID/TMCI1 P64/FTIC/TMO0 P63/FTIB/TMRI0 P62/FTIA P61/FTOA P60/FTCI/TMCI0 P77 to P70 AN7 to AN0 System clock (o) output Expanded data bus control output (RD, WR, AS) o output or general input General input/output Trigger input to A/D converter (ADTRG), external interrupt input (IRQ2 to IRQ0), or general input/output Serial communication interface input/output (TxD,RxD, SCK) or general input/output 16-bit free-running timer input/output (FTCI, FTOA, FTIA, FTIB, FTIC, FTID, FTOB), 8-bit timer 0/1 input/output (TMCI0, TMO0, TMRI0, TMCI1, TMO1, TMRI1) or general input/output Port 6 * 8-bit I/O port Port 7 * 8-bit input port Analog input to A/D converter (AN7 to AN0) or general input 92 7.2 Port 1 7.2.1 Overview Port 1 is an 8-bit input/output port with the pin configuration shown in figure 7-1. The pin functions differ depending on the operating mode. Port 1 has built-in, software-controllable MOS input pull-up transistors that can be used in modes 2 and 3. Pins in port 1 can drive one TTL load and a 90-pF capacitive load. They can also drive LEDs and darlington transistors. Port 1 pins P17/A7 P16/A6 P15/A5 Port 1 P14/A4 P13/A3 P12/A2 P11/A1 P10/A0 Pin configuration in mode 1 (expanded mode with on-chip ROM disabled) A7 (output) A6 (output) A5 (output) A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) Pin configuration in mode 2 (expanded mode with on-chip ROM enabled) A7 (output)/P17 (input) A6 (output)/P16 (input) A5 (output)/P15 (input) A4 (output)/P14 (input)) A3 (output)/P13 (input) A2 (output)/P12 (input) A1 (output)/P11 (input) A0 (output)/P10 (input) Pin configuration in mode 3 (single-chip mode) P17 (input/output) P16 (input/output) P15 (input/output) P14 (input/output) P13 (input/output) P12 (input/output) P11 (input/output) P10 (input/output) Figure 7-1 Port 1 Pin Configuration 93 7.2.2 Register Configuration and Descriptions Table 7-2 summarizes the port 1 registers. Table 7-2 Port 1 Registers Name Port 1 data direction register Port 1 data register Port 1 input pull-up control register Abbreviation P1DDR P1DR P1PCR Read/Write W R/W R/W Initial Value H'FF (mode 1) H'00 (modes 2 and 3) H'00 H'00 Address H'FFB0 H'FFB2 H'FFAC Port 1 Data Direction Register (P1DDR) Bit Mode 1 Initial value Read/Write Modes 2 and 3 Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 7 6 5 4 3 2 1 0 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR P1DDR controls the input/output direction of each pin in port 1. Mode 1: The P1DDR values are fixed at 1. Port 1 consists of lower address output pins. P1DDR values cannot be modified and are always read as 1. In hardware standby mode, the address bus is in the high-impedance state. Mode 2: A pin in port 1 is used for address output if the corresponding P1DDR bit is set to 1, and for general input if this bit is cleared to 0. Mode 3: A pin in port 1 is used for general output if the corresponding P1DDR bit is set to 1, and for general input if this bit is cleared to 0. In modes 2 and 3, P1DDR is a write-only register. Read data is invalid. If read, all bits always read 1. P1DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a P1DDR bit is set to 1, the corresponding pin remains in the output state. 94 Port 1 Data Register (P1DR) Bit Initial value Read/Write 7 P1 7 0 R/W 6 P1 6 0 R/W 5 P1 5 0 R/W 4 P1 4 0 R/W 3 P1 3 0 R/W 2 P1 2 0 R/W 1 P1 1 0 R/W 0 P1 0 0 R/W P1DR is an 8-bit register that stores data for pins P17 to P10. When a P1DDR bit is set to 1, if port 1 is read, the value in P1DR is obtained directly, regardless of the actual pin state. When a P1DDR bit is cleared to 0, if port 1 is read the pin state is obtained. P1DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. Port 1 Input Pull-Up Control Register (P1PCR) Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR P1PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 1. If a P1DDR bit is cleared to 0 (designating input) and the corresponding P1PCR bit is set to 1, the input pull-up transistor is turned on. P1PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 95 7.2.3 Pin Functions in Each Mode Port 1 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Mode 1: In mode 1 (expanded mode with on-chip ROM disabled), port 1 is automatically used for lower address output (A7 to A0). Figure 7-2 shows the pin functions in mode 1. A7 (output) A6 (output) A5 (output) Port 1 A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) Figure 7-2 Pin Functions in Mode 1 (Port 1) 96 Mode 2: In mode 2 (expanded mode with on-chip ROM enabled), port 1 can provide lower address output pins and general input pins. Each pin becomes a lower address output pin if its P1DDR bit is set to 1, and a general input pin if this bit is cleared to 0. Following a reset, all pins are input pins. To be used for address output, their P1DDR bits must be set to 1. Figure 7-3 shows the pin functions in mode 2. When P1DDR = 1 A7 (output) A6 (output) A5 (output) Port 1 A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) When P1DDR = 0 P17 (input) P16 (input) P15 (input) P14 (input) P13 (input) P12 (input) P11 (input) P10 (input) Figure 7-3 Pin Functions in Mode 2 (Port 1) 97 Mode 3: In mode 3 (single-chip mode), the input or output direction of each pin can be selected individually. A pin becomes a general input pin when its P1DDR bit is cleared to 0 and a general output pin when this bit is set to 1. Figure 7-4 shows the pin functions in mode 3. P17 (input/output) P16 (input/output) P15 (input/output) Port 1 P14 (input/output) P13 (input/output) P12 (input/output) P11 (input/output) P10 (input/output) Figure 7-4 Pin Functions in Mode 3 (Port 1) 7.2.4 Input Pull-Up Transistors Port 1 has built-in programmable input pull-up transistors that are available in modes 2 and 3. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode 2 or 3, set the corresponding P1PCR bit to 1 and clear the corresponding P1DDR bit to 0. P1PCR is cleared to H'00 by a reset and in hardware standby mode, turning all input pull-ups off. In software standby mode, the previous state is maintained. Table 7-3 indicates the states of the input pull-up transistors in each operating mode. Table 7-3 States of Input Pull-Up Transistors (Port 1) Mode 1 2 3 Reset Off Off Off Hardware Standby Off Off Off Software Standby Off On/off On/off Other Operating Modes Off On/off On/off Notes: Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P1PCR = 1 and P1DDR = 0, but off otherwise. 98 7.3 Port 2 7.3.1 Overview Port 2 is an 8-bit input/output port with the pin configuration shown in figure 7-5. The pin functions differ depending on the operating mode. Port 2 has built-in, software-controllable MOS input pull-up transistors that can be used in modes 2 and 3. Pins in port 2 can drive one TTL load and a 90-pF capacitive load. They can also drive LEDs and darlington transistors. Pin configuration in mode 1 (expanded mode with on-chip ROM disabled) A15 (output) A14 (output) A13 (output) A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) Pin configuration in mode 2 (expanded mode with on-chip ROM enabled) A15 (output)/P27 (input) A14 (output)/P26 (input) A13 (output)/P25 (input) A12 (output)/P24 (input) A11 (output)/P23 (input) A10 (output)/P22 (input) A9 (output)/P21 (input) A8 (output)/P20 (input) Port 2 pins P27/A15 P26/A14 P25/A13 Port 2 P24/A12 P23/A11 P22/A10 P21/A9 P20/A8 Pin configuration in mode 3 (single-chip mode) P27 (input/output) P26 (input/output) P25 (input/output) P24 (input/output) P23 (input/output) P22 (input/output) P21 (input/output) P20 (input/output) Figure 7-5 Port 2 Pin Configuration 99 7.3.2 Register Configuration and Descriptions Table 7-4 summarizes the port 2 registers. Table 7-4 Port 2 Registers Name Port 2 data direction register Port 2 data register Port 2 input pull-up control register Abbreviation P2DDR P2DR P2PCR Read/Write W R/W R/W Initial Value H'FF (mode 1) H'00 (modes 2 and 3) H'00 H'00 Address H'FFB1 H'FFB3 H'FFAD Port 2 Data Direction Register (P2DDR) Bit Mode 1 Initial value Read/Write Modes 2 and 3 Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 1 -- 7 6 5 4 3 2 1 0 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR P2DDR controls the input/output direction of each pin in port 2. Mode 1: The P2DDR values are fixed at 1. Port 2 consists of upper address output pins. P2DDR values cannot be modified and are always read as 1. In hardware standby mode, the address bus is in the high-impedance state. Mode 2: A pin in port 2 is used for address output if the corresponding P2DDR bit is set to 1, and for general input if this bit is cleared to 0. Mode 3: A pin in port 2 is used for general output if the corresponding P2DDR bit is set to 1, and for general input if this bit is cleared to 0. In modes 2 and 3, P2DDR is a write-only register. Read data is invalid. If read, all bits always read 1. P2DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a P2DDR bit is set to 1, the corresponding pin remains in the output state. 100 Port 2 Data Register (P2DR) Bit Initial value Read/Write 7 P27 0 R/W 6 P26 0 R/W 5 P25 0 R/W 4 P24 0 R/W 3 P23 0 R/W 2 P22 0 R/W 1 P21 0 R/W 0 P20 0 R/W P2DR is an 8-bit register that stores data for pins P27 to P20. When a P2DDR bit is set to 1, if port 2 is read, the value in P2DR is obtained directly, regardless of the actual pin state. When a P2DDR bit is cleared to 0, if port 2 is read the pin state is obtained. P2DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. Port 2 Input Pull-Up Control Register (P2PCR) Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR P2PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 2. If a P2DDR bit is cleared to 0 (designating input) and the corresponding P2PCR bit is set to 1, the input pull-up transistor is turned on. P2PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 101 7.3.3 Pin Functions in Each Mode Port 2 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Mode 1: In mode 1 (expanded mode with on-chip ROM disabled), port 2 is automatically used for upper address output (A15 to A8). Figure 7-6 shows the pin functions in mode 1. A15 (output) A14 (output) A13 (output) Port 2 A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) Figure 7-6 Pin Functions in Mode 1 (Port 2) 102 Mode 2: In mode 2 (expanded mode with on-chip ROM enabled), port 2 can provide upper address output pins and general input pins. Each pin becomes an upper address output pin if its P2DDR bit is set to 1, and a general input pin if this bit is cleared to 0. Following a reset, all pins are input pins. To be used for address output, their P2DDR bits must be set to 1. Figure 7-7 shows the pin functions in mode 2. When P2DDR = 1 A15 (output) A14 (output) A13 (output) Port 2 A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) When P2DDR = 0 P27 (input) P26 (input) P25 (input) P24 (input) P23 (input) P22 (input) P21 (input) P20 (input) Figure 7-7 Pin Functions in Mode 2 (Port 2) 103 Mode 3: In mode 3 (single-chip mode), the input or output direction of each pin can be selected individually. A pin becomes a general input pin when its P2DDR bit is cleared to 0, and a general output pin when this bit is set to 1. Figure 7-8 shows the pin functions in mode 3. P27 (input/output) P26 (input/output) P25 (input/output) Port 2 P24 (input/output) P23 (input/output) P22 (input/output) P21 (input/output) P20 (input/output) Figure 7-8 Pin Functions in Mode 3 (Port 2) 104 7.3.4 Input Pull-Up Transistors Port 2 has built-in programmable input pull-up transistors that are available in modes 2 and 3. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode 2 or 3, set the corresponding P2PCR bit to 1 and clear the corresponding P2DDR bit to 0. P2PCR is cleared to H'00 by a reset and in hardware standby mode, turning all input pull-ups off. In software standby mode, the previous state is maintained. Table 7-5 indicates the states of the input pull-up transistors in each operating mode. Table 7-5 States of Input Pull-Up Transistors (Port 2) Mode 1 2 3 Reset Off Off Off Hardware Standby Off Off Off Software Standby Off On/off On/off Other Operating Modes Off On/off On/off Notes: Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P2PCR = 1 and P2DDR = 0, but off otherwise. 105 7.4 Port 3 7.4.1 Overview Port 3 is an 8-bit input/output port with the pin configuration shown in Figure 7-9. The pin functions differ depending on the operating mode. Port 3 has built-in, software-controllable MOS input pull-up transistors that can be used in mode 3. Pins in port 3 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington pair. Port 3 pins P37/D7 P36/D6 P35/D5 Port 3 P34/D4 P33/D3 P32/D2 P31/D1 P30/D0 Pin configuration in mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled) D7 (input/output) D6 (input/output) D5 (input/output) D4 (input/output) D3 (input/output) D2 (input/output) D1 (input/output) D0 (input/output) Pin configuration in mode 3 (single-chip mode) P37 (input/output) P36 (input/output) P35 (input/output) P34 (input/output) P33 (input/output) P32 (input/output) P31 (input/output) P30 (input/output) Figure 7-9 Port 3 Pin Configuration 106 7.4.2 Register Configuration and Descriptions Table 7-6 summarizes the port 3 registers. Table 7-6 Port 3 Registers Name Port 3 data direction register Port 3 data register Port 3 input pull-up control register Abbreviation P3DDR P3DR P3PCR Read/Write W R/W R/W Initial Value H'00 H'00 H'00 Address H'FFB4 H'FFB6 H'FFAE Port 3 Data Direction Register (P3DDR) Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P3 7 DDR P3 6 DDR P3 5 DDR P3 4 DDR P3 3 DDR P3 2 DDR P3 1 DDR P3 0 DDR P3DDR is an 8-bit readable/writable register that controls the input/output direction of each pin in port 3. P3DDR is a write-only register. Read data is invalid. If read, all bits always read 1. Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled), the input/output directions designated by P3DDR are ignored. Port 3 automatically consists of the input/output pins of the 8-bit data bus (D7 to D0). The data bus is in the high-impedance state during reset, and during hardware and software standby. Mode 3: A pin in port 3 is used for general output if the corresponding P3DDR bit is set to 1, and for general input if this bit is cleared to 0. P3DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a P3DDR bit is set to 1, the corresponding pin remains in the output state. 107 Port 3 Data Register (P3DR) Bit Initial value Read/Write 7 P37 0 R/W 6 P36 0 R/W 5 P35 0 R/W 4 P34 0 R/W 3 P33 0 R/W 2 P32 0 R/W 1 P31 0 R/W 0 P30 0 R/W P3DR is an 8-bit register that stores data for pins P37 to P30. When a P3DDR bit is set to 1, if port 3 is read, the value in P3DR is obtained directly, regardless of the actual pin state. When a P3DDR bit is cleared to 0, if port 3 is read the pin state is obtained. P3DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. Port 3 Input Pull-Up Control Register (P3PCR) Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR P3PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 3. If a P3DDR bit is cleared to 0 (designating input) and the corresponding P3PCR bit is set to 1, the input pull-up transistor is turned on. P3PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. The input pull-ups cannot be used in slave mode (when the host interface is enabled). 108 7.4.3 Pin Functions in Each Mode Port 3 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled), port 3 is automatically used for the input/output pins of the data bus (D7 to D0). Figure 7-10 shows the pin functions in modes 1 and 2. Modes 1 and 2 D7 (input/output) D6 (input/output) D5 (input/output) Port 3 D4 (input/output) D3 (input/output) D2 (input/output) D1 (input/output) D0 (input/output) Figure 7-10 Pin Functions in Modes 1 and 2 (Port 3) 109 Mode 3: In mode 3 (single-chip mode), the input or output direction of each pin can be selected individually. A pin becomes a general input pin when its P3DDR bit is cleared to 0, and a general output pin when this bit is set to 1. Figure 7-11 shows the pin functions in mode 3. P37 (input/output) P36 (input/output) P35 (input/output) Port 3 P34 (input/output) P33 (input/output) P32 (input/output) P31 (input/output) P30 (input/output) Figure 7-11 Pin Functions in Mode 3 (Port 3) 7.4.4 Input Pull-Up Transistors Port 3 has built-in programmable input pull-up transistors that are available in mode 3. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode 3, set the corresponding P3PCR bit to 1 and clear the corresponding P3DDR bit to 0. P3PCR is cleared to H'00 by a reset and in hardware standby mode, turning all input pull-ups off. In software standby mode, the previous state is maintained. Table 7-7 indicates the states of the input pull-up transistors in each operating mode. Table 7-7 States of Input Pull-Up Transistors (Port 3) Mode 1 2 3 Reset Off Off Off Hardware Standby Off Off Off Software Standby Off Off On/off Other Operating Modes Off Off On/off Notes: Off: The input pull-up transistor is always off. On/off: The input pull-up transistor is on if P3PCR = 1 and P3DDR = 0, but off otherwise. 110 7.5 Port 4 7.5.1 Overview Port 4 is an 8-bit input/output port that is multiplexed with interrupt input pins (IRQ0 to IRQ2), input/output pins for bus control signals (RD, WR, AS, WAIT), an input pin (ADTRG) for the A/D converter, and an output pin (o) for the system clock. Figure 7-12 shows the pin configuration of port 4. Pins in port 4 can drive one TTL load and a 90-pF capacitive load. Port 4 pins P47/WAIT P46/o P45/AS Port 4 P44/WR P43/RD P42/IRQ0 P41/IRQ1 Pin configuration in mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded mode with on-chip ROM enabled) P47/WAIT (input) o (output) AS (output) WR (output) RD (output) P42 (input/output)/IRQ0 (input) P41 (input/output)/IRQ1 (input) P40/IRQ2/ADTRG (input) P40 (input/output)/IRQ2 (input)/ADTRG (input) Pin configuration in mode 3 (single-chip mode) P47 (input/output) P46 (intput)/o (output) P45 (input/output) P44 (input/output) P43 (input/output) P42 (input/output)/IRQ0 (input) P41 (input/output)/IRQ1 (input) P40 (input/output)/IRQ2 /ADTRG (input) Figure 7-12 Port 4 Pin Configuration 111 7.5.2 Register Configuration and Descriptions Table 7-8 summarizes the port 4 registers. Table 7-8 Port 4 Registers Name Port 4 data direction register Port 4 data register Abbreviation P4DDR P4DR Read/Write W R/W*1 Initial Value H'40 (modes 1 and 2) H'00 (mode 3) Undetermined*2 Address H'FFB5 H'FFB7 Notes: 1. Bit 6 is read-only. 2. Bit 6 is undetermined. Other bits are initially 0. Port 4 Data Direction Register (P4DDR) 7 Bit Modes 1, 2 Initial value Read/Write Mode 3 Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 1 -- 0 W 0 W 0 W 0 W 0 W 0 W 6 5 4 3 2 1 0 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR P4DDR is an 8-bit readable/writable register that controls the input/output direction of each pin in port 4. A pin functions as an output pin if the corresponding P4DDR bit is set to 1, and as an input pin if this bit is cleared to 0. In modes 1 and 2, P46DDR is fixed at 1 and cannot be modified. P4DDR is a write-only register. Read data is invalid. If read, all bits always read 1. P4DDR is initialized by a reset and in hardware standby mode. The initial value is H'40 in modes 1 and 2, and H'00 in mode 3. In software standby mode P4DDR retains its existing values, so if a transition to software standby mode occurs while a P4DDR bit is set to 1, the corresponding pin remains in the output state. 112 Port 4 Data Register (P4DR) Bit Initial value Read/Write 7 P47 0 R/W 6 P46 * R 5 P45 0 R/W 4 P44 0 R/W 3 P43 0 R/W 2 P42 0 R/W 1 P41 0 R/W 0 P40 0 R/W Note: * Determined by the level at pin P46. P4DR is an 8-bit register that stores data for pins P46 to P40. When a P4DDR bit is set to 1, if port 4 is read, the value in P4DR is obtained directly, regardless of the actual pin state, except for P46. When a P4DDR bit is cleared to 0, if port 4 is read the pin state is obtained. This also applies to pins used by on-chip supporting modules and for bus control signals. P46 always returns the pin state. P4DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 7.5.3 Pin Functions Port 4 has one set of pin functions in modes 1 and 2, and a different set of pin functions in mode 3. The pins are multiplexed with IRQ0 to IRQ2 input, bus control signal input/output, A/D converter input, and system clock (o) output. Table 7-9 indicates the pin functions of port 4. Table 7-9 Port 4 Pin Functions Pin P47/WAIT Pin Functions and Selection Method Bit P47DDR, the operating mode, and the wait mode determined by WSCR select the pin function as follws Operating mode Wait mode P47DDR Pin function P46/o WAIT used -- WAIT input Modes 1 and 2 WAIT not used (WMS1=0, WMS0=1) 0 P47 input 1 P47 output 0 P47 input Mode 3 -- 1 P47 output Bit P46DDR and the operating mode select the pin function as follows Operating mode P46DDR Pin function Modes 1 and 2 Always 1 o output 0 P46 input Mode 3 1 o output 113 Table 7-19 Port 4 Pin Functions (cont) Pin Pin Functions and Selection Method Bit P45DDR and the operating mode select the pin function as follows Operating mode P45DDR Pin function P44/WR Modes 1 and 2 -- AS output 0 P45 input Mode 3 1 P45 output P45/AS Bit P44DDR and the operating mode select the pin function as follows Operating mode P44DDR Pin function Modes 1 and 2 -- WR output 0 P44 input Mode 3 1 P44 output P43/RD Bit P43DDR and the operating mode select the pin function as follows Operating mode P43DDR Pin function Modes 1 and 2 -- RD output 0 P43 input Mode 3 1 P43 output P42/IRQ0 P42DDR Pin function 0 P42 input IRQ0 input IRQ0 input can be used when bit IRQ0E is set to 1 in IER P41/IRQ1 P41DDR Pin function 0 P41 input IRQ1 input IRQ1 input can be used when bit IRQ1E is set to 1 in IER P40/IRQ2/ ADTRG P40DDR Pin function 0 P40 input IRQ2 input and ADTRG input IRQ2 input can be used when bit IRQ2E is set to 1 in IER ADTRG input can be used when bit TRGE is set to 1 in ADCR 1 P40 output 1 P41 output 1 P42 output 114 7.6 Port 5 7.6.1 Overview Port 5 is a 3-bit input/output port that is multiplexed with input/output pins (TxD, RxD, SCK) of serial communication interface. The port 5 pin functions are the same in all operating modes. Figure 7-13 shows the pin configuration of port 5. Pins in port 5 can drive one TTL load and a 30-pF capacitive load. They can also drive a darlington pair. Port 5 pins P52 (input/output)/SCK (input/output) Port 5 P51 (input/output)/RxD (input) P50 (input/output)/TxD (output) Figure 7-13 Port 5 Pin Configuration 7.6.2 Register Configuration and Descriptions Table 7-10 summarizes the port 5 registers. Table 7-10 Port 5 Registers Name Port 5 data direction register Port 5 data register Abbreviation P5DDR P5DR Read/Write W R/W Initial Value H'F8 H'F8 Address H'FFB8 H'FFBA 115 Port 5 Data Direction Register (P5DDR) 7 Bit Initial value Read/Write -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 0 W 1 0 W 0 0 W P5 2 DDR P5 1 DDR P5 0 DDR P5DDR is an 8-bit register that controls the input/output direction of each pin in port 5. A pin functions as an output pin if the corresponding P5DDR bit is set to 1, and as an input pin if this bit is cleared to 0. P5DDR is a write-only register. Read data is invalid. If read, all bits always read 1. P5DDR is initialized to H'F8 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a P5DDR bit is set to 1, the corresponding pin remains in the output state. If a transition to software standby mode occurs while port 5 is being used by the SCI, the SCI will be initialized, so the pin will revert to general-purpose input/output, controlled by P5DDR and P5DR. Port 5 Data Register (P5DR) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 P52 0 R/W 1 P51 0 R/W 0 P50 0 R/W P5DR is an 8-bit register that stores data for pins P52 to P50. Bits 7 to 3 are reserved. They cannot be modified, and are always read as 1. When a P5DDR bit is set to 1, if port 5 is read, the value in P5DR is obtained directly, regardless of the actual pin state. When a P5DDR bit is cleared to 0, if port 5 is read the pin state is obtained. This also applies to pins used as SCI pins. P5DR is initialized to H'F8 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 116 7.6.3 Pin Functions Port 5 has the same pin functions in each operating mode. All pins can also be used as SCI input/output pins. Table 7-11 indicates the pin functions of port 5. Table 7-11 Port 5 Pin Functions Pin P52/SCK Pin Functions and Selection Method Bit C/A in SMR of SCI, bits CKE0 and CKE1 in SCR of SCI, and bit P52DDR select the pin function as follows CKE1 C/A CKE0 P52DDR Pin function 0 P52 input 0 1 P52 output 0 1 -- SCK output 0 1 -- -- SCK output 1 -- -- -- SCK input P51/RxD Bit RE in SCR of SCI and bit P51DDR select the pin function as follows RE P51DDR Pin function 0 P51 input 0 1 P51 output 1 -- RxD input P50/TxD Bit TE in SCR of SCI and bit P50DDR select the pin function as follows TE P50DDR Pin function 0 P50 input 0 1 P50 output 1 -- TxD output 117 7.7 Port 6 7.7.1 Overview Port 6 is an 8-bit input/output port that is multiplexed with input/output pins (FTOA, FTOB, FTIA to FTID, FTCI) of the 16-bit free-running timer (FRT) and with input/output pins (TMRI0, TMRI1, TMCI0, TMCI1, TMO0, TMO1) of 8-bit timers 0 and 1. The port 6 pin functions are the same in all operating modes. Figure 7-14 shows the pin configuration of port 6. Pins in port 6 can drive one TTL load and a 90-pF capacitive load. They can also drive a darlington pair. Port 6 pins P67 (input/output)/TMO1 (output) P66 (input/output)/FTOB (output)/TMRI1 (input) P65 (input/output)/FTID (input)/TMCI1 (input) Port 6 P64 (input/output)/FTIC (input)/TMO0 (output) P63 (input/output)/FTIB (input)/TMRI0 (input) P62 (input/output)/FTIA (input) P61 (input/output)/FTOA (output) P60 (input/output)/FTCI (input)/TMCI0 (input) Figure 7-14 Port 6 Pin Configuration 118 7.7.2 Register Configuration and Descriptions Table 7-12 summarizes the port 6 registers. Table 7-12 Port 6 Registers Name Port 6 data direction register Port 6 data register Abbreviation P6DDR P6DR Read/Write W R/W Initial Value H'00 H'00 Address H'FFB9 H'FFBB Port 6 Data Direction Register (P6DDR) Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR P6DDR is an 8-bit readable/writable register that controls the input/output direction of each pin in port 6. A pin functions as an output pin if the corresponding P6DDR bit is set to 1, and as an input pin if this bit is cleared to 0. P6DDR is a write-only register. Read data is invalid. If read, all bits always read 1. P6DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values, so if a transition to software standby mode occurs while a P6DDR bit is set to 1, the corresponding pin remains in the output state. If a transition to software standby mode occurs while port 6 is being used by an on-chip supporting module (for example, for 8-bit timer output), the on-chip supporting module will be initialized, so the pin will revert to general-purpose input/output, controlled by P6DDR and P6DR. 119 Port 6 Data Register (P6DR) Bit Initial value Read/Write 7 P67 0 R/W 6 P66 0 R/W 5 P65 0 R/W 4 P64 0 R/W 3 P63 0 R/W 2 P62 0 R/W 1 P61 0 R/W 0 P60 0 R/W P6DR is an 8-bit register that stores data for pins P67 to P60. When a P6DDR bit is set to 1, if port 6 is read, the value in P6DR is obtained directly, regardless of the actual pin state. When a P6DDR bit is cleared to 0, if port 6 is read the pin state is obtained. This also applies to pins used by on-chip supporting modules. P6DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its existing values. 120 7.7.3 Pin Functions Port 6 has the same pin functions all operating modes. The pins are multiplexed with FRT input/output, and 8-bit timer input/output. Table 7-13 indicates the pin functions of port 6. Table 7-13 Port 6 Pin Functions Pin P67/TMO1 Pin Functions and Selection Method Bits OS3 to OS0 in TCSR of 8-bit timer 1, and bit P67DDR, select the pin function as follows OS3 to 0 P67DDR Pin function P66/FTOB/ TMRI1 0 P67 input All 0 1 P67 output Not all 0 -- TMO1 output Bit OEB in TOCR of the FRT and bit P66DDR select the pin function as follows OEB P66DDR Pin function 0 P66 input 0 1 P66 output TMRI1 input TMRI1 input is usable when bits CCLR1 and CCLR0 are both set to 1 in TCR of 8-bit timer 1 0 FTOB output 1 1 P65/FTID/ TMCI1 P65DDR Pin function 0 P65 input 1 P65 output FTID input or TMCI1 input TMCI1 input is usable when bits CKS2 to CKS0 in TCR of 8-bit timer 1 select an external clock source P64/FTIC/ TMO0 Bits OS3 to OS0 in TCSR of 8-bit timer 0 and bit P64DDR select the pin function as follows OS3 to 0 P64DDR Pin function 0 P64 input All 0 1 P64 output FTIC input 0 TMO0 output Not all 0 1 121 Table 7-13 Port 6 Pin Functions (cont) Pin P63/FTIB/ TMRI0 Pin Functions and Selection Method P63DDR Pin function 0 P63 input 1 P63 output FTIB input or TMRI0 input TMRI0 input is usable when bits CCLR1 and CCLR0 are both set to 1 in TCR of 8bit timer 0 P62/FTIA P62DDR Pin function 0 P62 input FTIA input P61/FTOA Bit OEA in TOCR of the FRT and bit P61DDR select the pin function as follows OEA P61DDR Pin function P60/FTCI/ TMCI0 0 P61 input 0 1 P61 output 0 FTOA output 1 1 1 P62 output P60DDR Pin function 0 P60 input 1 P60 output FTCI input or TMCI0 input FTCI input is usable when bits CKS1 and CKS0 in TCR of the FRT select an external clock source TMCI0 input is usable when bits CKS2 to CKS0 in TCR of 8-bit timer 0 select an external clock source 122 7.8 Port 7 7.8.1 Overview Port 7 is an 8-bit input port that also provides the analog input pins for the A/D converter. The pin functions are the same in all modes. Figure 7-15 shows the pin configuration of port 7. Port 7 pins P77 (input)/AN7 (input) P76 (input)/AN6 (input) P75 (input)/AN5 (input) Port 7 P74 (input)/AN4 (input) P73 (input)/AN3 (input) P72 (input)/AN2 (input) P71 (input)/AN1 (input) P70 (input)/AN0 (input) Figure 7-15 Port 7 Pin Configuration 123 7.8.2 Register Configuration and Descriptions Table 7-14 summarizes the port 7 registers. Port 7 is an input port, so there is no data direction register. Table 7-14 Port 7 Register Name Port 7 input register Abbreviation P7PIN Read/Write R Initial Value Undetermined Address H'FFBE Port 7 Input Register (P7PIN) Bit Initial value Read/Write 7 P77 --* R 6 P76 --* R 5 P75 --* R 4 P74 --* R 3 P73 --* R 2 P72 --* R 1 P71 --* R 0 P70 --* R Note: * Depends on the levels of pins P77 to P70. When P7PIN is read, the pin states are always read. P7PIN is a read-only register and cannot be written to. 124 Section 8 16-Bit Free-Running Timer 8.1 Overview The H8/3297 Series has an on-chip 16-bit free-running timer (FRT) module that uses a 16-bit freerunning counter as a time base. Applications of the FRT module include rectangular-wave output (up to two independent waveforms), input pulse width measurement, and measurement of external clock periods. 8.1.1 Features The features of the free-running timer module are listed below. * Selection of four clock sources The free-running counter can be driven by an internal clock source (oP/2, oP/8, or oP/32), or an external clock input (enabling use as an external event counter). * Two independent comparators Each comparator can generate an independent waveform. * Four input capture channels The current count can be captured on the rising or falling edge (selectable) of an input signal. The four input capture registers can be used separately, or in a buffer mode. * Counter can be cleared under program control The free-running counters can be cleared on compare-match A. * Seven independent interrupts Compare-match A and B, input capture A to D, and overflow interrupts are requested independently. 125 8.1.2 Block Diagram Figure 8-1 shows a block diagram of the free-running timer. External clock source FTCI Clock select Internal clock sources oP/2 oP/8 oP/32 Clock Comparematch A OCRA (H/L) Comparator A FTOA0 FTOB0 Overflow Clear Comparator B Bus interface FRC (H/L) Internal data bus Comparematch B OCRB (H/L) Control logic FTIA FTIB FTIC FTID TCSR TIER TCR TOCR ICIA ICIB ICIC ICID OCIA OCIB FOVI Capture ICRA (H/L) ICRB (H/L) ICRC (H/L) ICRD (H/L) Interrupt signals Legend Free-running counter (16 bits) FRC: Output compare register A, B (16 bits) OCRA, B: ICRA, B, C, D: Input capture register A, B, C, D (16 bits) TCSR: Timer control/status register (8 bits) TIER: Timer interrupt enable register (8 bits) TCR: Timer control register (8 bits) TOCR: Timer output compare control register (8 bits) Figure 8-1 Block Diagram of 16-Bit Free-Running Timer 126 Module data bus 8.1.3 Input and Output Pins Table 8-1 lists the input and output pins of the free-running timer module. Table 8-1 Input and Output Pins of Free-Running Timer Module Name Counter clock input Output compare A Output compare B Input capture A Input capture B Input capture C Input capture D Abbreviation FTCI FTOA FTOB FTIA FTIB FTIC FTID I/O Input Output Output Input Input Input Input Function Input of external free-running counter clock signal Output controlled by comparator A Output controlled by comparator B Trigger for capturing current count into input capture register A Trigger for capturing current count into input capture register B Trigger for capturing current count into input capture register C Trigger for capturing current count into input capture register D 8.1.4 Register Configuration Table 8-2 lists the registers of the free-running timer module. Table 8-2 Register Configuration Name Timer interrupt enable register Timer control/status register Free-running counter (high) Free-running counter (low) Output compare register A/B (high)*2 Abbreviation TIER TCSR FRC (H) FRC (L) OCRA/B (H) OCRA/B (L) TCR TOCR ICRA (H) ICRA (L) R/W R/W R/(W)*1 R/W R/W R/W R/W R/W R/W R R Initial Value H'01 H'00 H'00 H'00 H'FF H'FF H'00 H'E0 H'00 H'00 Address H'FF90 H'FF91 H'FF92 H'FF93 H'FF94*2 H'FF95*2 H'FF96 H'FF97 H'FF98 H'FF99 Output compare register A/B (low)*2 Timer control register Timer output compare control register Input capture register A (high) Input capture register A (low) Notes: 1. Software can write a 0 to clear bits 7 to 1, but cannot write a 1 in these bits. 2. OCRA and OCRB share the same addresses. Access is controlled by the OCRS bit in TOCR. 127 Table 8-2 Register Configuration (cont.) Name Input capture register B (high) Input capture register B (low) Input capture register C (high) Input capture register C (low) Input capture register D (high) Input capture register D (low) Abbreviation ICRB (H) ICRB (L) ICRC (H) ICRC (L) ICRD (H) ICRD (L) R/W R R R R R R Initial Value H'00 H'00 H'00 H'00 H'00 H'00 Address H'FF9A H'FF9B H'FF9C H'FF9D H'FF9E H'FF9F 8.2 Register Descriptions 8.2.1 Free-Running Counter (FRC) Bit Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a clock source. The clock source is selected by the clock select 1 and 0 bits (CKS1 and CKS0) of the timer control register (TCR). When FRC overflows from H'FFFF to H'0000, the overflow flag (OVF) in the timer control/status register (TCSR) is set to 1. Because FRC is a 16-bit register, a temporary register (TEMP) is used when FRC is written or read. See section 8.3, CPU Interface, for details. FRC is initialized to H'0000 at a reset and in the standby modes. It can also be cleared by comparematch A. 128 8.2.2 Output Compare Registers A and B (OCRA and OCRB) Bit Initial value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually compared with the value in the FRC. When a match is detected, the corresponding output compare flag (OCFA or OCFB) is set in the timer control/status register (TCSR). In addition, if the output enable bit (OEA or OEB) in the timer output compare control register (TOCR) is set to 1, when the output compare register and FRC values match, the logic level selected by the output level bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Following a reset, the FTOA and FTOB output levels are 0 until the first compare-match. OCRA and OCRB share the same address. They are differentiated by the OCRS bit in TOCR. A temporary register (TEMP) is used for write access, as explained in section 8.3, CPU Interface. OCRA and OCRB are initialized to H'FFFF at a reset and in the standby modes. 8.2.3 Input Capture Registers A to D (ICRA to ICRD) Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R There are four input capture registers A to D, each of which is a 16-bit read-only register. When the rising or falling edge of the signal at an input capture pin (FTIA to FTID) is detected, the current FRC value is copied to the corresponding input capture register (ICRA to ICRD).* At the same time, the corresponding input capture flag (ICFA to ICFD) in the timer control/status register (TCSR) is set to 1. The input capture edge is selected by the input edge select bits (IEDGA to IEDGD) in the timer control register (TCR). Note: * The FRC contents are transferred to the input capture register regardless of the value of the input capture flag (ICFA/B/C/D). Input capture can be buffered by using the input capture registers in pairs. When the BUFEA bit in TCR is set to 1, ICRC is used as a buffer register for ICRA as shown in figure 8-2. When an FTIA input is received, the old ICRA contents are moved into ICRC, and the new FRC count is copied into ICRA. 129 BUFEA IEDGA IEDGC FTIA Edge detect and capture signal generating circuit ICRC ICRA FRC BUFEA: IEDGA: IEDGC: ICRC: ICRA: FRC: Buffer enable A Input edge select A Input edge select C Input capture register C Input capture register A Free-running counter Figure 8-2 Input Capture Buffering Similarly, when the BUFEB bit in TCR is set to 1, ICRD is used as a buffer register for ICRB. When input capture is buffered, if the two input edge bits are set to different values (IEDGA IEDGC or IEDGB IEDGD), then input capture is triggered on both the rising and falling edges of the FTIA or FTIB input signal. If the two input edge bits are set to the same value (IEDGA = IEDGC or IEDGB = IEDGD), then input capture is triggered on only one edge. See table 8-3. Table 8-3 Buffered Input Capture Edge Selection (Example) IEDGA 0 0 1 1 IEDGC 0 1 0 1 Captured on rising edge of input capture A (FTIA) Input Capture Edge Captured on falling edge of input capture A (FTIA) (Initial value) Captured on both rising and falling edges of input capture A (FTIA) Because the input capture registers are 16-bit registers, a temporary register (TEMP) is used when they are read. See section 8.3, CPU Interface, for details. To ensure input capture, the width of the input capture pulse should be at least 1.5 system clock periods (1.5*o). When triggering is enabled on both edges, the input capture pulse width should be at least 2.5 system clock periods. The input capture registers are initialized to H'0000 at a reset and in the standby modes. 130 8.2.4 Timer Interrupt Enable Register (TIER) Bit Initial value Read/Write 7 ICIAE 0 R/W 6 ICIBE 0 R/W 5 ICICE 0 R/W 4 ICIDE 0 R/W 3 OCIAE 0 R/W 2 OCIBE 0 R/W 1 OVIE 0 R/W 0 -- 1 -- The TIER is an 8-bit readable/writable register that enables and disables interrupts. The TIER is initialized to H'01 at a reset and in the standby modes. Bit 7--Input Capture Interrupt A Enable (ICIAE): This bit selects whether to request input capture interrupt A (ICIA) when input capture flag A (ICFA) in the timer status/control register (TCSR) is set to 1. Bit 7 ICIAE 0 1 Description Input capture interrupt request A (ICIA) is disabled. Input capture interrupt request A (ICIA) is enabled. (Initial value) Bit 6--Input Capture Interrupt B Enable (ICIBE): This bit selects whether to request input capture interrupt B (ICIB) when input capture flag B (ICFB) in TCSR is set to 1. Bit 6 ICIBE 0 1 Description Input capture interrupt request B (ICIB) is disabled. Input capture interrupt request B (ICIB) is enabled. (Initial value) Bit 5--Input Capture Interrupt C Enable (ICICE): This bit selects whether to request input capture interrupt C (ICIC) when input capture flag C (ICFC) in TCSR is set to 1. Bit 5 ICICE 0 1 Description Input capture interrupt request C (ICIC) is disabled. Input capture interrupt request C (ICIC) is enabled. (Initial value) 131 Bit 4--Input Capture Interrupt D Enable (ICIDE): This bit selects whether to request input capture interrupt D (ICID) when input capture flag D (ICFD) in TCSR is set to 1. Bit 4 ICIDE 0 1 Description Input capture interrupt request D (ICID) is disabled. Input capture interrupt request D (ICID) is enabled. (Initial value) Bit 3--Output Compare Interrupt A Enable (OCIAE): This bit selects whether to request output compare interrupt A (OCIA) when output compare flag A (OCFA) in TCSR is set to 1. Bit 3 OCIAE 0 1 Description Output compare interrupt request A (OCIA) is disabled. Output compare interrupt request A (OCIA) is enabled. (Initial value) Bit 2--Output Compare Interrupt B Enable (OCIBE): This bit selects whether to request output compare interrupt B (OCIB) when output compare flag B (OCFB) in TCSR is set to 1. Bit 2 OCIBE 0 1 Description Output compare interrupt request B (OCIB) is disabled. Output compare interrupt request B (OCIB) is enabled. (Initial value) Bit 1--Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a freerunning timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1. Bit 1 OVIE 0 1 Description Timer overflow interrupt request (FOVI) is disabled. Timer overflow interrupt request (FOVI) is enabled. (Initial value) Bit 0--Reserved: This bit cannot be modified and is always read as 1. 132 8.2.5 Timer Control/Status Register (TCSR) Bit Initial value Read/Write 7 ICFA 0 R/(W)* 6 ICFB 0 R/(W)* 5 ICFC 0 R/(W)* 4 ICFD 0 R/(W)* 3 OCFA 0 R/(W)* 2 OCFB 0 R/(W)* 1 OVF 0 R/(W)* 0 OCLRA 0 R/W Note: * Software can write a 0 in bits 7 to 1 to clear the flags, but cannot write a 1 in these bits. TCSR is an 8-bit readable and partially writable* register that contains the seven interrupt flags and specifies whether to clear the counter on compare-match A (when the FRC and OCRA values match). TCSR is initialized to H'00 at a reset and in the standby modes. Timing is described in section 8.4, Operation. Bit 7--Input Capture Flag A (ICFA): This status bit is set to 1 to flag an input capture A event. If BUFEA = 0, ICFA indicates that the FRC value has been copied to ICRA. If BUFEA = 1, ICFA indicates that the old ICRA value has been moved into ICRC and the new FRC value has been copied to ICRA. ICFA must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 7 ICFA 0 1 Description To clear ICFA, the CPU must read ICFA after it has been set to 1, then write a 0 in this bit. (Initial value) This bit is set to 1 when an FTIA input signal causes the FRC value to be copied to ICRA. Bit 6--Input Capture Flag B (ICFB): This status bit is set to 1 to flag an input capture B event. If BUFEB = 0, ICFB indicates that the FRC value has been copied to ICRB. If BUFEB = 1, ICFB indicates that the old ICRB value has been moved into ICRD and the new FRC value has been copied to ICRB. ICFB must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 6 ICFB 0 1 Description To clear ICFB, the CPU must read ICFB after it has been set to 1, then write a 0 in this bit. (Initial value) This bit is set to 1 when an FTIB input signal causes the FRC value to be copied to ICRB. 133 Bit 5--Input Capture Flag C (ICFC): This status bit is set to 1 to flag input of a rising or falling edge of FTIC as selected by the IEDGC bit. When BUFEA = 0, this indicates capture of the FRC count in ICRC. When BUFEA = 1, however, the FRC count is not captured, so ICFC becomes simply an external interrupt flag. In other words, the buffer mode frees FTIC for use as a generalpurpose interrupt signal (which can be enabled or disabled by the ICICE bit). ICFC must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 5 ICFC 0 1 Description To clear ICFC, the CPU must read ICFC after it has been set to 1, then write a 0 in this bit. This bit is set to 1 when an FTIC input signal is received. (Initial value) Bit 4--Input Capture Flag D (ICFD): This status bit is set to 1 to flag input of a rising or falling edge of FTID as selected by the IEDGD bit. When BUFEB = 0, this indicates capture of the FRC count in ICRD. When BUFEB = 1, however, the FRC count is not captured, so ICFD becomes simply an external interrupt flag. In other words, the buffer mode frees FTID for use as a generalpurpose interrupt signal (which can be enabled or disabled by the ICIDE bit). ICFD must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 4 ICFD 0 1 Description To clear ICFD, the CPU must read ICFD after it has been set to 1, then write a 0 in this bit. This bit is set to 1 when an FTID input signal is received. (Initial value) Bit 3--Output Compare Flag A (OCFA): This status flag is set to 1 when the FRC value matches the OCRA value. This flag must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 3 OCFA 0 1 Description To clear OCFA, the CPU must read OCFA after it has been set to 1, then write a 0 in this bit. This bit is set to 1 when FRC = OCRA. (Initial value) 134 Bit 2--Output Compare Flag B (OCFB): This status flag is set to 1 when the FRC value matches the OCRB value. This flag must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 2 OCFB 0 1 Description To clear OCFB, the CPU must read OCFB after it has been set to 1, then write a 0 in this bit. This bit is set to 1 when FRC = OCRB. (Initial value) Bit 1--Timer Overflow Flag (OVF): This status flag is set to 1 when the FRC overflows (changes from H'FFFF to H'0000). This flag must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 1 OVF 0 1 Description To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0 in this bit. This bit is set to 1 when FRC changes from H'FFFF to H'0000. (Initial value) Bit 0--Counter Clear A (CCLRA): This bit selects whether to clear the FRC at compare-match A (when the FRC and OCRA values match). Bit 0 CCLRA 0 1 Description The FRC is not cleared. The FRC is cleared at compare-match A. (Initial value) 8.2.6 Timer Control Register (TCR) Bit Initial value Read/Write 7 IEDGA 0 R/W 6 IEDGB 0 R/W 5 IEDGC 0 R/W 4 IEDGD 0 R/W 3 BUFEA 0 R/W 2 BUFEB 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the FRC clock source. TCR is initialized to H'00 at a reset and in the standby modes. 135 Bit 7--Input Edge Select A (IEDGA): This bit selects the rising or falling edge of the input capture A signal (FTIA). Bit 7 IEDGA 0 1 Description Input capture A events are recognized on the falling edge of FTIA. Input capture A events are recognized on the rising edge of FTIA. (Initial value) Bit 6--Input Edge Select B (IEDGB): This bit selects the rising or falling edge of the input capture B signal (FTIB). Bit 6 IEDGB 0 1 Description Input capture B events are recognized on the falling edge of FTIB. Input capture B events are recognized on the rising edge of FTIB. (Initial value) Bit 5--Input Edge Select C (IEDGC): This bit selects the rising or falling edge of the input capture C signal (FTIC). Bit 5 IEDGC 0 1 Description Input capture C events are recognized on the falling edge of FTIC. Input capture C events are recognized on the rising edge of FTIC. (Initial value) Bit 4--Input Edge Select D (IEDGD): This bit selects the rising or falling edge of the input capture D signal (FTID). Bit 4 IEDGD 0 1 Description Input capture D events are recognized on the falling edge of FTID. Input capture D events are recognized on the rising edge of FTID. (Initial value) Bit 3--Buffer Enable A (BUFEA): This bit selects whether to use ICRC as a buffer register for ICRA. Bit 3 BUFEA 0 1 Description ICRC is used for input capture C. ICRC is used as a buffer register for input capture A. (Initial value) 136 Bit 2--Buffer Enable B (BUFEB): This bit selects whether to use ICRD as a buffer register for ICRB. Bit 2 BUFEB 0 1 Description ICRD is used for input capture D. ICRD is used as a buffer register for input capture B. (Initial value) Bits 1 and 0--Clock Select (CKS1 and CKS0): These bits select external clock input or one of three internal clock sources for FRC. External clock pulses are counted on the rising edge of signals input to pin FTCI. Bit 1 CKS1 0 0 1 1 Bit 0 CKS0 0 1 0 1 Description oP/2 internal clock source oP/8 internal clock source oP/32 internal clock source External clock source (rising edge) (Initial value) 8.2.7 Timer Output Compare Control Register (TOCR) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 OCRS 0 R/W 3 OEA 0 R/W 2 OEB 0 R/W 1 OLVLA 0 R/W 0 OLVLB 0 R/W TOCR is an 8-bit readable/writable register that enables output from the output compare pins, selects the output levels, and switches access between output compare registers A and B. TOCR is initialized to H'E0 at a reset and in the standby modes. Bits 7 to 5--Reserved: These bits cannot be modified and are always read as 1. Bit 4--Output Compare Register Select (OCRS): OCRA and OCRB share the same address. When this address is accessed, the OCRS bit selects which register is accessed. This bit does not affect the operation of OCRA or OCRB. Bit 4 OCRS 0 1 Description OCRA is selected. OCRB is selected. (Initial value) 137 Bit 3--Output Enable A (OEA): This bit enables or disables output of the output compare A signal (FTOA). Bit 3 OEA 0 1 Description Output compare A output is disabled. Output compare A output is enabled. (Initial value) Bit 2--Output Enable B (OEB): This bit enables or disables output of the output compare B signal (FTOB). Bit 2 OEB 0 1 Description Output compare B output is disabled. Output compare B output is enabled. (Initial value) Bit 1--Output Level A (OLVLA): This bit selects the logic level to be output at the FTOA pin when the FRC and OCRA values match. Bit 1 OLVLA 0 1 Description A 0 logic level is output for compare-match A. A 1 logic level is output for compare-match A. (Initial value) Bit 0--Output Level B (OLVLB): This bit selects the logic level to be output at the FTOB pin when the FRC and OCRB values match. Bit 0 OLVLB 0 1 Description A 0 logic level is output for compare-match B. A 1 logic level is output for compare-match B. (Initial value) 138 8.3 CPU Interface The free-running counter (FRC), output compare registers (OCRA and OCRB), and input capture registers (ICRA to ICRD) are 16-bit registers, but they are connected to an 8-bit data bus. When the CPU accesses these registers, to ensure that both bytes are written or read simultaneously, the access is performed using an 8-bit temporary register (TEMP). These registers are written and read as follows: * Register Write When the CPU writes to the upper byte, the byte of write data is placed in TEMP. Next, when the CPU writes to the lower byte, this byte of data is combined with the byte in TEMP and all 16 bits are written in the register simultaneously. * Register Read When the CPU reads the upper byte, the upper byte of data is sent to the CPU and the lower byte is placed in TEMP. When the CPU reads the lower byte, it receives the value in TEMP. Programs that access these registers should normally use word access. Equivalently, they may access first the upper byte, then the lower byte by two consecutive byte accesses. Data will not be transferred correctly if the bytes are accessed in reverse order, or if only one byte is accessed. Figure 8-3 shows the data flow when FRC is accessed. The other registers are accessed in the same way. As an exception, when the CPU reads OCRA or OCRB, it reads both the upper and lower bytes directly, without using TEMP. Coding Examples To write the contents of general register R0 to OCRA: To transfer the contents of ICRA to general register R0: MOV.W MOV.W R0, @OCRA @ICRA, R0 139 (1) Upper byte write Module data bus CPU writes data H'AA Bus interface TEMP [H'AA] FRCH [ ] (2) Lower byte write FRCL [ ] CPU writes data H'55 Bus interface Module data bus TEMP [H'AA] FRCH [H'AA] FRCL [H'55] Figure 8-3 (a) Write Access to FRC (when CPU Writes H'AA55) 140 (1) Upper byte read CPU reads data H'AA Bus interface Module data bus TEMP [H'55] FRCH [H'AA] FRCL [H'55] (2) Lower byte read Module data bus CPU reads data H'55 Bus interface TEMP [H'55] FRCH [ ] FRCL [ ] Figure 8-3 (b) Read Access to FRC (when FRC Contains H'AA55) 141 8.4 Operation 8.4.1 FRC Incrementation Timing FRC increments on a pulse generated once for each period of the selected (internal or external) clock source. The clock source is selected by bits CKS0 and CKS1 in the TCR. Internal Clock: The internal clock sources (oP/2, oP/8, oP/32) are created from the system clock (o) by a prescaler. FRC increments on a pulse generated from the falling edge of the prescaler output. See figure 8-4. o Internal clock FRC clock pulse FRC N-1 N N+1 Figure 8-4 Increment Timing for Internal Clock Source 142 External Clock: If external clock input is selected, FRC increments on the rising edge of the FTCI clock signal. Figure 8-5 shows the increment timing. The pulse width of the external clock signal must be at least 1.5 system clock (o) periods. The counter will not increment correctly if the pulse width is shorter than 1.5 system clock periods. o FTCI FRC clock pulse FRC N N+1 Figure 8-5 Increment Timing for External Clock Source 143 8.4.2 Output Compare Timing When a compare-match occurs, the logic level selected by the output level bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Figure 8-6 shows the timing of this operation for compare-match A. o FRC N N+1 N N+1 OCRA Internal comparematch A signal N N Clear* OLVLA FTOA Note: * Cleared by software Figure 8-6 Timing of Output Compare A 144 8.4.3 FRC Clear Timing If the CCLRA bit in TCSR is set to 1, the FRC is cleared when compare-match A occurs. Figure 8-7 shows the timing of this operation. o Internal comparematch A signal FRC N H'0000 Figure 8-7 Clearing of FRC by Compare-Match A 145 8.4.4 Input Capture Timing (1) Input Capture Timing: An internal input capture signal is generated from the rising or falling edge of the signal at the input capture pin FTIx (x = A, B, C, D), as selected by the corresponding IEDGx bit in TCR. Figure 8-8 shows the usual input capture timing when the rising edge is selected (IEDGx = 1). o Input data FTI pin Internal input capture signal Figure 8-8 Input Capture Timing (Usual Case) If the upper byte of ICRA/B/C/D is being read when the corresponding input capture signal arrives, the internal input capture signal is delayed by one state. Figure 8-9 shows the timing for this case. ICR upper byte read cycle T1 o T2 T3 Input at FTI pin Internal input capture signal Figure 8-9 Input Capture Timing (1-State Delay Due to ICRA/B/C/D Read) 146 (2) Buffered Input Capture Timing: ICRC and ICRD can operate as buffers for ICRA and ICRB. Figure 8-10 shows how input capture operates when ICRA and ICRC are used in buffer mode and IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDG A = 1 and IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA. o FTIA Internal input capture signal FRC n n+1 N N+1 ICRA M n n N ICRC m M M n Figure 8-10 Buffered Input Capture with Both Edges Selected 147 When ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and if the ICIEC bit is set, an interrupt will be requested. The FRC value will not be transferred to ICRC, however. In buffered input capture, if the upper byte of either of the two registers to which data will be transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input signal arrives, input capture is delayed by one system clock (o). Figure 8-11 shows the timing when BUFEA = 1. Read cycle: CPU reads upper byte of ICRA or ICRC T1 o Input at FTIA pin Internal input capture signal T2 T3 Figure 8-11 Input Capture Timing (1-State Delay, Buffer Mode) 148 8.4.5 Timing of Input Capture Flag (ICF) Setting The input capture flag ICFx (x = A, B, C, D) is set to 1 by the internal input capture signal. Figure 8-12 shows the timing of this operation. o Internal input capture signal ICF FRC N ICR N Figure 8-12 Setting of Input Capture Flag 149 8.4.6 Setting of Output Compare Flags A and B (OCFA and OCFB) The output compare flags are set to 1 by an internal compare-match signal generated when the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last state in which the two values match, just before FRC increments to a new value. Accordingly, when the FRC and OCR values match, the compare-match signal is not generated until the next period of the clock source. Figure 8-13 shows the timing of the setting of the output compare flags. o FRC N N+1 OCRA or OCRB N Internal comparematch signal OCFA or OCFB Figure 8-13 Setting of Output Compare Flags 150 8.4.7 Setting of FRC Overflow Flag (OVF) The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000). Figure 8-14 shows the timing of this operation. o FRC H'FFFF H'0000 Internal overflow signal OVF Figure 8-14 Setting of Overflow Flag (OVF) 8.5 Interrupts The free-running timer can request seven interrupts (three types): input capture A to D (ICIA, ICIB, ICIC, ICID), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt controller for each interrupt. Table 8-4 lists information about these interrupts. Table 8-4 Free-Running Timer Interrupts Interrupt ICIA ICIB ICIC ICID OCIA OCIB FOVI Description Requested by ICFA Requested by ICFB Requested by ICFC Requested by ICFD Requested by OCFA Requested by OCFB Requested by OVF Low Priority High 151 8.6 Sample Application In the example below, the free-running timer is used to generate two square-wave outputs with a 50% duty cycle and arbitrary phase relationship. The programming is as follows: (1) The CCLRA bit in TCSR is set to 1. (2) Each time a compare-match interrupt occurs, software inverts the corresponding output level bit in TOCR (OLVLA or OLVLB). FRC H'FFFF OCRA OCRB H'0000 FTOA Clear counter FTOB Figure 8-15 Square-Wave Output (Example) 152 8.7 Usage Notes Application programmers should note that the following types of contention can occur in the freerunning timer. (1) Contention between FRC Write and Clear: If an internal counter clear signal is generated during the T3 state of a write cycle to the lower byte of the free-running counter, the clear signal takes priority and the write is not performed. Figure 8-16 shows this type of contention. Write cycle: CPU write to lower byte of FRC T1 T2 T3 o Internal address bus Internal write signal FRC address FRC clear signal FRC N H'0000 Figure 8-16 FRC Write-Clear Contention 153 (2) Contention between FRC Write and Increment: If an FRC increment pulse is generated during the T3 state of a write cycle to the lower byte of the free-running counter, the write takes priority and FRC is not incremented. Figure 8-17 shows this type of contention. Write cycle: CPU write to lower byte of FRC T1 T2 T3 o Internal address bus FRC address Internal write signal FRC clock pulse FRC N M Write data Figure 8-17 FRC Write-Increment Contention 154 (3) Contention between OCR Write and Compare-Match: If a compare-match occurs during the T3 state of a write cycle to the lower byte of OCRA or OCRB, the write takes priority and the compare-match signal is inhibited. Figure 8-18 shows this type of contention. Write cycle: CPU write to lower byte of OCRA or OCRB T1 T2 T3 o Intenal address bus OCR address Internal write signal FRC N N+1 OCRA or OCRB N M Write data Compare-match A or B signal Inhibited Figure 8-18 Contention between OCR Write and Compare-Match 155 (4) Incrementation Caused by Changing of Internal Clock Source: When an internal clock source is changed, the changeover may cause FRC to increment. This depends on the time at which the clock select bits (CKS1 and CKS0) are rewritten, as shown in table 8-5. The pulse that increments FRC is generated at the falling edge of the internal clock source. If clock sources are changed when the old source is high and the new source is low, as in case no. 3 in table 8-5, the changeover generates a falling edge that triggers the FRC increment clock pulse. Switching between an internal and external clock source can also cause FRC to increment. Table 8-5 Effect of Changing Internal Clock Sources No. 1 Description Low low: CKS1 and CKS0 are rewritten while both clock sources are low. Timing Old clock source New clock source FRC clock pulse FRC N CKS rewrite N+1 2 Low high: CKS1 and CKS0 are rewritten while old clock source is low and new clock source is high. Old clock source New clock source FRC clock pulse FRC N N+1 N+2 CKS rewrite 156 Table 8-5 Effect of Changing Internal Clock Sources (cont) No. 3 Description High low: CKS1 and CKS0 are rewritten while old clock source is high and new clock source is low. Timing Old clock source New clock source * FRC clock pulse FRC N N+1 CKS rewrite N+2 4 High high: CKS1 and CKS0 are rewritten while both clock sources are high. Old clock source New clock source FRC clock pulse FRC N N+1 N+2 CKS rewrite Note: * The switching of clock sources is regarded as a falling edge that increments FRC. 157 Section 9 8-Bit Timers 9.1 Overview The H8/3297 Series includes an 8-bit timer module with two channels (numbered 0 and 1). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare-match events. One of the many applications of the 8-bit timer module is to generate a rectangular-wave output with an arbitrary duty cycle. 9.1.1 Features The features of the 8-bit timer module are listed below. * Selection of seven clock sources The counters can be driven by one of six internal clock signals or an external clock input (enabling use as an external event counter). * Selection of three ways to clear the counters The counters can be cleared on compare-match A or B, or by an external reset signal. * Timer output controlled by two time constants The timer output signal in each channel is controlled by two independent time constants, enabling the timer to generate output waveforms with an arbitrary duty cycle, or PWM waveforms. * Three independent interrupts Compare-match A and B and overflow interrupts can be requested independently. 159 9.1.2 Block Diagram Figure 9-1 shows a block diagram of one channel in the 8-bit timer module. External clock source TMCI Internal clock sources Channel 0 oP/2 oP/8 oP/32 oP/64 oP/256 oP/1024 Clock Channel 1 oP/2 oP/8 oP/64 oP/128 oP/1024 oP/2048 Clock select TCORA Compare-match A Comparator A TMO TMRI Clear Comparator B Control logic Compare-match B TCORB Overflow Module data bus TCNT Internal data bus TCSR TCR CMIA CMIB OVI Interrupt signals TCR: TCSR: TCORA: TCORB: TCNT: Timer control register (8 bits) Timer control status register (8 bits) Time constant register A (8 bits) Time constant register B (8 bits) Timer counter Figure 9-1 Block Diagram of 8-Bit Timer (1 Channel) 160 Bus interface 9.1.3 Input and Output Pins Table 9-1 lists the input and output pins of the 8-bit timer. Table 9-1 Input and Output Pins of 8-Bit Timer Abbreviation* Name Timer output Timer clock input Timer reset input Channel 0 TMO0 TMCI0 TMRI0 Channel 1 TMO1 TMCI1 TMRI1 I/O Output Input Input Function Output controlled by compare-match External clock source for the counter External reset signal for the counter Note: * In this manual, the channel subscript has been deleted, and only TMO TMCI, and TMRI are used. 9.1.4 Register Configuration Table 9-2 lists the registers of the 8-bit timer module. Each channel has an independent set of registers. Table 9-2 8-Bit Timer Registers Channel 0 Name Timer control register Timer control/status register Time constant register A Time constant register B Timer counter 1 Timer control register Timer control/status register Time constant register A Time constant register B Timer counter 0, 1 Serial/timer control register Abbreviation TCR TCSR TCORA TCORB TCNT TCR TCSR TCORA TCORB TCNT STCR R/W R/W Initial Value Address H'00 H'FFC8 H'FFC9 H'FFCA H'FFCB H'FFCC H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFC3 R/(W)* H'10 R/W R/W R/W R/W H'FF H'FF H'00 H'00 R/(W)* H'10 R/W R/W R/W R/W H'FF H'FF H'00 H'F8 Note: * Software can write a 0 to clear bits 7 to 5, but cannot write a 1 in these bits. 161 9.2 Register Descriptions 9.2.1 Timer Counter (TCNT) Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Each timer counter (TCNT) is an 8-bit up-counter that increments on a pulse generated from an internal or external clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) of the timer control register (TCR). The CPU can always read or write the timer counter. The timer counter can be cleared by an external reset input or by an internal compare-match signal generated at a compare-match event. Clock clear bits 1 and 0 (CCLR1 and CCLR0) of the timer control register select the method of clearing. When a timer counter overflows from H'FF to H'00, the overflow flag (OVF) in the timer control/status register (TCSR) is set to 1. The timer counters are initialized to H'00 at a reset and in the standby modes. 9.2.2 Time Constant Registers A and B (TCORA and TCORB) Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W TCORA and TCORB are 8-bit readable/writable registers. The timer count is continually compared with the constants written in these registers (except during the T3 state of a write cycle to TCORA or TCORB). When a match is detected, the corresponding compare-match flag (CMFA or CMFB) is set in the timer control/status register (TCSR). The timer output signal is controlled by these compare-match signals as specified by output select bits 3 to 0 (OS3 to OS0) in the timer control/status register (TCSR). TCORA and TCORB are initialized to H'FF at a reset and in the standby modes. 162 9.2.3 Timer Control Register (TCR) Bit Initial value Read/Write 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W TCR is an 8-bit readable/writable register that selects the clock source and the time at which the timer counter is cleared, and enables interrupts. TCR is initialized to H'00 at a reset and in the standby modes. For timing diagrams, see section 9.3, Operation. Bit 7--Compare-match Interrupt Enable B (CMIEB): This bit selects whether to request compare-match interrupt B (CMIB) when compare-match flag B (CMFB) in the timer control/status register (TCSR) is set to 1. Bit 7 CMIEB 0 1 Description Compare-match interrupt request B (CMIB) is disabled. Compare-match interrupt request B (CMIB) is enabled. (Initial value) Bit 6--Compare-match Interrupt Enable A (CMIEA): This bit selects whether to request compare-match interrupt A (CMIA) when compare-match flag A (CMFA) in TCSR is set to 1. Bit 6 CMIEA 0 1 Description Compare-match interrupt request A (CMIA) is disabled. Compare-match interrupt request A (CMIA) is enabled. (Initial value) 163 Bit 5--Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a timer overflow interrupt (OVI) when the overflow flag (OVF) in TCSR is set to 1. Bit 5 OVIE 0 1 Description The timer overflow interrupt request (OVI) is disabled. The timer overflow interrupt request (OVI) is enabled. (Initial value) Bits 4 and 3--Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select how the timer counter is cleared: by compare-match A or B or by an external reset input (TMRI). Bit 4 CCLR1 0 0 1 1 Bit 3 CCLR0 0 1 0 1 Description Not cleared. Cleared on compare-match A. Cleared on compare-match B. Cleared on rising edge of external reset input signal. (Initial value) 164 Bits 2, 1, and 0--Clock Select (CKS2, CKS1, and CKS0): These bits and bits ICKS1 and ICKS0 in the serial/timer control register (STCR) select the internal or external clock source for the timer counter. Six internal clock sources, derived by prescaling the system clock, are available for each timer channel. For internal clock sources the counter is incremented on the falling edge of the internal clock. For an external clock source, these bits can select whether to increment the counter on the rising or falling edge of the clock input (TMCI), or on both edges. TCR STCR Bit 2 Bit 1 Bit 0 Bit 1 Bit 0 Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 0 1 -- -- -- -- -- -- -- -- -- -- -- -- 0 1 0 1 0 1 -- -- -- -- -- 0 1 0 1 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- No clock source (timer stopped) (Initial value) oP/8 internal clock, counted on falling edge oP/2 internal clock, counted on falling edge oP/64 internal clock, counted on falling edge oP/32 internal clock, counted on falling edge oP/1024 internal clock, counted on falling edge oP/256 internal clock, counted on falling edge No clock source (timer stopped) External clock source, counted on rising edge External clock source, counted on falling edge External clock source, counted on both rising and falling edges No clock source (timer stopped) (Initial value) oP/8 internal clock, counted on falling edge oP/2 internal clock, counted on falling edge oP/64 internal clock, counted on falling edge oP/128 internal clock, counted on falling edge oP/1024 internal clock, counted on falling edge oP/2048 internal clock, counted on falling edge No clock source (timer stopped) External clock source, counted on rising edge External clock source, counted on falling edge External clock source, counted on both rising and falling edges 165 9.2.4 Timer Control/Status Register (TCSR) Bit Initial value Read/Write 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 -- 1 -- 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W Note: * Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits. TCSR is an 8-bit readable and partially writable register that indicates compare-match and overflow status and selects the effect of compare-match events on the timer output signal. TCSR is initialized to H'10 at a reset and in the standby modes. Bit 7--Compare-Match Flag B (CMFB): This status flag is set to 1 when the timer count matches the time constant set in TCORB. CMFB must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 7 CMFB 0 1 Description To clear CMFB, the CPU must read CMFB after it has been set to 1 then write a 0 in this bit. This bit is set to 1 when TCNT = TCORB. (Initial value) Bit 6--Compare-Match Flag A (CMFA): This status flag is set to 1 when the timer count matches the time constant set in TCORA. CMFA must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 6 CMFA 0 1 Description To clear CMFA, the CPU must read CMFA after it has been set to 1, then write a 0 in this bit. This bit is set to 1 when TCNT = TCORA. (Initial value) 166 Bit 5--Timer Overflow Flag (OVF): This status flag is set to 1 when the timer count overflows (changes from H'FF to H'00). OVF must be cleared by software. It is set by hardware, however, and cannot be set by software. Bit 5 OVF 0 1 Description To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0 in this bit. This bit is set to 1 when TCNT changes from H'FF to H'00. (Initial value) Bit 4--Reserved: This bit is always read as 1. It cannot be written. Bits 3 to 0--Output Select 3 to 0 (OS3 to OS0): These bits specify the effect of TCOR-TCNT compare-match events on the timer output signal (TMO). Bits OS3 and OS2 control the effect of compare-match B on the output level. Bits OS1 and OS0 control the effect of compare-match A on the output level. If compare-match A and B occur simultaneously, any conflict is resolved according to the following priority order: toggle > 1 output > 0 output. When all four output select bits are cleared to 0 the timer output signal is disabled. After a reset, the timer output is 0 until the first compare-match event. Bit 3 OS3 0 0 1 1 Bit 1 OS1 0 0 1 1 Bit 2 OS2 0 1 0 1 Bit 0 OS0 0 1 0 1 Description No change when compare-match B occurs. Output changes to 0 when compare-match B occurs. Output changes to 1 when compare-match B occurs. Output inverts (toggles) when compare-match B occurs. (Initial value) Description No change when compare-match A occurs. Output changes to 0 when compare-match A occurs. Output changes to 1 when compare-match A occurs. Output inverts (toggles) when compare-match A occurs. (Initial value) 167 9.2.5 Serial/Timer Control Register (STCR) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 MPE 0 R/W 1 ICKS1 0 R/W 0 ICKS0 0 R/W STCR is an 8-bit readable/writable register that controls the operating mode of the serial communication interface, and selects internal clock sources for the timer counters. STCR is initialized to H'F8 at a reset. Bits 7 to 3--Reserved: These bits cannot be modified and are always read as 1. Bit 2--Multiprocessor Enable (MPE): Controls the operating mode of serial communication interfaces 0 and 1. For details, see section 11, Serial Communication Interface. Bits 1 and 0--Internal Clock Source Select 1 and 0 (ICKS1 and ICKS0): These bits and bits CKS2 to CKS0 in the TCR select clock sources for the timer counters. For details, see section 9.2.3, Timer Control Register. 168 9.3 Operation 9.3.1 TCNT Incrementation Timing The timer counter increments on a pulse generated once for each period of the selected (internal or external) clock source. Internal Clock: Internal clock sources are created from the system clock by a prescaler. The counter increments on an internal TCNT clock pulse generated from the falling edge of the prescaler output, as shown in figure 9-2. Bits CKS2 to CKS0 of TCR and bits ICKS1 and ICKS0 of STCR can select one of the six internal clocks. o Internal clock TCNT clock pulse TCNT N-1 N N+1 Figure 9-2 Count Timing for Internal Clock Input 169 External Clock: If external clock input (TMCI) is selected, the timer counter can increment on the rising edge, the falling edge, or both edges of the external clock signal. Figure 9-3 shows incrementation on both edges of the external clock signal. The external clock pulse width must be at least 1.5 system clock (o) periods for incrementation on a single edge, and at least 2.5 system clock periods for incrementation on both edges. The counter will not increment correctly if the pulse width is shorter than these values. o External clock source (TMCI) TCNT clock pulse TCNT N-1 N N+1 Figure 9-3 Count Timing for External Clock Input 170 9.3.2 Compare Match Timing (1) Setting of Compare-Match Flags A and B (CMFA and CMFB): The compare-match flags are set to 1 by an internal compare-match signal generated when the timer count matches the time constant in TCORA or TCORB. The compare-match signal is generated at the last state in which the match is true, just before the timer counter increments to a new value. Accordingly, when the timer count matches one of the time constants, the compare-match signal is not generated until the next period of the clock source. Figure 9-4 shows the timing of the setting of the compare-match flags. o TCNT N N+1 TCOR N Internal comparematch signal CMF Figure 9-4 Setting of Compare-Match Flags 171 (2) Output Timing: When a compare-match event occurs, the timer output changes as specified by the output select bits (OS3 to OS0) in the TCSR. Depending on these bits, the output can remain the same, change to 0, change to 1, or toggle. Figure 9-5 shows the timing when the output is set to toggle on compare-match A. o Internal comparematch A signal Timer output (TMO) Figure 9-5 Timing of Timer Output (3) Timing of Compare-Match Clear: Depending on the CCLR1 and CCLR0 bits in TCR, the timer counter can be cleared when compare-match A or B occurs. Figure 9-6 shows the timing of this operation. o Internal comparematch signal TCNT N H'00 Figure 9-6 Timing of Compare-Match Clear 172 9.3.3 External Reset of TCNT When the CCLR1 and CCLR0 bits in TCR are both set to 1, the timer counter is cleared on the rising edge of an external reset input. Figure 9-7 shows the timing of this operation. The timer reset pulse width must be at least 1.5 system clock (o) periods. o External reset input (TMRI) Internal clear pulse TCNT N-1 N H'00 Figure 9-7 Timing of External Reset 9.3.4 Setting of TCSR Overflow Flag (OVF) The overflow flag (OVF) is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure 9-8 shows the timing of this operation. o TCNT H'FF H'00 Internal overflow signal OVF Figure 9-8 Setting of Overflow Flag (OVF) 173 9.4 Interrupts Each channel in the 8-bit timer can generate three types of interrupts: compare-match A and B (CMIA and CMIB), and overflow (OVI). Each interrupt can be enabled or disabled by an enable bit in TCR. Independent signals are sent to the interrupt controller for each interrupt. Table 9-3 lists information about these interrupts. Table 9-3 8-Bit Timer Interrupts Interrupt CMIA CMIB OVI Description Requested by CMFA Requested by CMFB Requested by OVF Low Priority High 9.5 Sample Application In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle. The control bits are set as follows: (1) In TCR, CCLR1 is cleared to 0 and CCLR0 is set to 1 so that the timer counter is cleared when its value matches the constant in TCORA. (2) In TCSR, bits OS3 to OS0 are set to 0110, causing the output to change to 1 on compare-match A and to 0 on compare-match B. With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a pulse width determined by TCORB. No software intervention is required. TCNT H'FF TCORA TCORB H'00 Clear counter TMO pin Figure 9-9 Example of Pulse Output 174 9.6 Usage Notes Application programmers should note that the following types of contention can occur in the 8-bit timer. 9.6.1 Contention between TCNT Write and Clear If an internal counter clear signal is generated during the T3 state of a write cycle to the timer counter, the clear signal takes priority and the write is not performed. Figure 9-10 shows this type of contention. Write cycle: CPU writes to TCNT T1 T2 T3 o Internal address bus Internal write signal TCNT address Counter clear signal TCNT N H'00 Figure 9-10 TCNT Write-Clear Contention 175 9.6.2 Contention between TCNT Write and Increment If a timer counter increment pulse is generated during the T3 state of a write cycle to the timer counter, the write takes priority and the timer counter is not incremented. Figure 9-11 shows this type of contention. Write cycle: CPU writes to TCNT T1 T2 T3 o Internal address bus TCNT address Internal write signal TCNT clock pulse TNCT N M Write data Figure 9-11 TCNT Write-Increment Contention 176 9.6.3 Contention between TCOR Write and Compare-Match If a compare-match occurs during the T3 state of a write cycle to TCOR, the write takes precedence and the compare-match signal is inhibited. Figure 9-12 shows this type of contention. Write cycle: CPU writes to TCOR T1 T2 T3 o Internal address bus TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare-match A or B signal Inhibited Figure 9-12 Contention between TCOR Write and Compare-Match 177 9.6.4 Contention between Compare-Match A and Compare-Match B If identical time constants are written in TCORA and TCORB, causing compare-match A and B to occur simultaneously, any conflict between the output selections for compare-match A and B is resolved by following the priority order in table 9-4. Table 9-4 Priority of Timer Output Output Selection Toggle 1 output 0 output No change Low Priority High 9.6.5 Incrementation Caused by Changing of Internal Clock Source When an internal clock source is changed, the changeover may cause the timer counter to increment. This depends on the time at which the clock select bits (CKS1, CKS0) are rewritten, as shown in table 9-5. The pulse that increments the timer counter is generated at the falling edge of the internal clock source signal. If clock sources are changed when the old source is high and the new source is low, as in case no. 3 in table 9-5, the changeover generates a falling edge that triggers the TCNT clock pulse and increments the timer counter. Switching between an internal and external clock source can also cause the timer counter to increment. 178 Table 9-5 Effect of Changing Internal Clock Sources No. 1 Description Low low*1 Timing Old clock source New clock source TCNT clock pulse TCNT N CKS rewrite N+1 2 Low high*2 Old clock source New clock source TCNT clock pulse TCNT N N+1 N+2 CKS rewrite Notes: 1. Including a transition from low to the stopped state (CKS1 = 0, CKS0 = 0), or a transition from the stopped state to low. 2. Including a transition from the stopped state to high. 179 Table 9-5 Effect of Changing Internal Clock Sources (cont) No. 3 Description High low*1 Timing chart Old clock source New clock source *2 TCNT clock pulse TCNT N N+1 CKS rewrite N+2 4 High high Old clock source New clock source TCNT clock pulse TCNT N N+1 N+2 CKS rewrite Notes: 1. Including a transition from high to the stopped state. 2. The switching of clock sources is regarded as a falling edge that increments TCNT. 180 Section 10 Watchdog Timer 10.1 Overview The H8/3297 Series has an on-chip watchdog timer (WDT) that can monitor system operation by resetting the CPU or generating a nonmaskable interrupt if a system crash allows the timer count to overflow. When this watchdog function is not needed, the watchdog timer module can be used as an interval timer. In interval timer mode, it requests an OVF interrupt at each counter overflow. 10.1.1 Features * * Selection of eight clock sources Selection of two modes: -- Watchdog timer mode -- Interval timer mode * Counter overflow generates an interrupt request or reset: -- Reset or NMI request in watchdog timer mode -- OVF interrupt request in interval timer mode 181 10.1.2 Block Diagram Figure 10-1 is a block diagram of the watchdog timer. Internal NMI (Watchdog timer mode) Interrupt signals OVF (Interval timer mode) Interrupt control Overflow Internal data bus Read/write control TCSR Internal reset Internal clock source Clock Clock select oP/2 oP/32 oP/64 oP/128 oP/256 oP/512 oP/2048 oP/4096 TCNT TCNT: Timer counter TCSR: Timer control/status register Figure 10-1 Block Diagram of Watchdog Timer 10.1.3 Register Configuration Table 10-1 lists information on the watchdog timer registers. Table 10-1 Register Configuration Addresses Name Timer control/status register Timer counter Abbreviation TCSR TCNT R/W R/(W)* R/W Initial Value H'18 H'00 Write H'FFA8 H'FFA8 Read H'FFA8 H'FFA9 Note: * Software can write a 0 to clear the status flag bits, but cannot write 1. 182 10.2 Register Descriptions 10.2.1 Timer Counter (TCNT) Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W TCNT is an 8-bit readable/writable up-counter. When the timer enable bit (TME) in the timer control/status register (TCSR) is set to 1, the timer counter starts counting pulses of an internal clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) in TCSR. When the count overflows (changes from H'FF to H'00), an overflow flag (OVF) in TCSR is set to 1. TCNT is initialized to H'00 at a reset and when the TME bit is cleared to 0. Note: TCNT is more difficult to write to than other registers. See Section 10.2.3, Register Access, for details. 10.2.2 Timer Control/Status Register (TCSR) Bit Initial value Read/Write 7 OVF 0 R/(W*) 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 -- 3 RST/NMI 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Note: * Software can write a 0 in bit 7 to clear the flag, but cannot write a 1 in this bit. TCSR is more difficult to write to than other registers. See Section 12.2.3, Register Access, for details. TCSR is an 8-bit readable/writable register that selects the timer mode and clock source and performs other functions. (TCSR is write-protected by a password. See section 10.2.3, Register Access, for details.) Bits 7 to 5 and bit 3 are initialized to 0 at a reset and in the standby modes. Bits 2 to 0 are initialized to 0 at a reset, but retain their values in the standby modes. 183 Bit 7--Overflow Flag (OVF): Indicates that the watchdog timer count has overflowed. Bit 7 OVF 0 1 Description To clear OVF, the CPU must read OVF when it is 1, then write 0 in this bit (Initial value) * Set to 1 when TENT changes from H'FF to H'00 * In interval timer mode or when the NMI interrupt is selected in watchdog timer mode Bit 6--Timer Mode Select (WT/IT): Selects whether to operate in watchdog timer mode or interval timer mode. When TCNT overflows, an OVF interrupt request is sent to the CPU in interval timer mode. For watchdog timer mode, a reset or NMI interrupt is requested. Bit 6 WT/IT 0 1 Description Interval timer mode (OVF request in case of overflow) Watchdog timer mode (reset or NMI request in case of overflow) (Initial value) Bit 5--Timer Enable (TME): Enables or disables the timer. Bit 5 TME 0 1 Description TCNT is initialized to H'00 and stopped TCNT runs and requests a reset or an interrupt when it overflows (Initial value) Bit 4--Reserved: This bit cannot be modified and is always read as 1. Bit 3: Reset or NMI Select (RST/NMI): Selects either an internal reset or the NMI function at watchdog timer overflow. Bit 3 RST/NMI 0 1 Description NMI function enabled Reset function enabled (Initial value) 184 Bits 2--0: Clock Select (CKS2-CKS0): These bits select one of eight clock sources obtained by dividing the system clock (o). The overflow interval is the time from when the watchdog timer counter begins counting from H'00 until an overflow occurs. In interval timer mode, OVF interrupts are requested at this interval. Bit 2 CKS2 0 0 0 0 1 1 1 1 Bit 1 CKS1 0 0 1 1 0 0 1 1 Bit 0 CKS0 0 1 0 1 0 1 0 1 Clock Source oP/2 oP/32 oP/64 oP/128 oP/256 oP/512 oP/2048 oP/4096 Overflow Interval (oP = 10 MHz) 51.2 s 819.2 s 1.6 ms 3.3 ms 6.6 ms 13.1 ms 52.4 ms 104.9 ms (Initial value) 10.2.3 Register Access The watchdog timer's TCNT and TCSR registers are more difficult to write than other registers. The procedures for writing and reading these registers are given below. Writing to TCNT and TCSR: Word access is required. Byte data transfer instructions cannot be used for write access. The TCNT and TCSR registers have the same write address. The write data must be contained in the lower byte of a word written at this address. The upper byte must contain H'5A (password for TCNT) or H'A5 (password for TCSR). See figure 10-2. The result of the access depicted in figure 10-2 is to transfer the write data from the lower byte to TCNT or TCSR. Writing to TCNT H'FFA8 15 H'5A 87 Write data 0 Writing to TCSR H'FFA8 15 H'A5 87 Write data 0 Figure 10-2 Writing to TCNT and TCSR 185 Reading TCNT and TCSR: The read addresses are H'FFA8 for TCSR and H'FFA9 for TCNT, as indicated in table 10-2. These two registers are read like other registers. Byte access instructions can be used. Table 10-2 Read Addresses of TCNT and TCSR Read Address H'FFA8 H'FFA9 Register TCSR TCNT 10.3 Operation 10.3.1 Watchdog Timer Mode The watchdog timer function begins operating when software sets the WT/IT and TME bits to 1 in TCSR. Thereafter, software should periodically rewrite the contents of the timer counter (normally by writing H'00) to prevent the count from overflowing. If a program crash allows the timer count to overflow, the entire chip is reset for 518 system clocks (518 o), or an NMI interrupt is requested. Figure 10-3 shows the operation. NMI requests from the watchdog timer have the same vector as NMI requests from the NMI pin. Avoid simultaneous handling of watchdog timer NMI requests and NMI requests from pin NMI. A reset from the watchdog timer has the same vector as an external reset from the RES pin. The reset source can be determined by the XRST bit in SYSCR. WDT overflow H'FF WT/IT = 1 TME = 1 TCNT count H'00 OVF = 1 WT/IT = 1 TME = 1 H'00 written to TCNT Reset 518 o H'00 written to TCNT Time t Figure 10-3 Operation in Watchdog Timer Mode 186 10.3.2 Interval Timer Mode Interval timer operation begins when the WT/IT bit is cleared to 0 and the TME bit is set to 1. In interval timer mode, an OVF request is generated each time the timer count overflows. This function can be used to generate OVF requests at regular intervals. See figure 10-4. H'FF TCNT count Time t H'00 WT/IT = 0 TME = 1 OVF request OVF request OVF request OVF request OVF request Figure 10-4 Operation in Interval Timer Mode 10.3.3 Setting the Overflow Flag The OVF bit is set to 1 when the timer count overflows. Simultaneously, the WDT module requests an internal reset, NMI, or OVF interrupt. The timing is shown in figure 10-5. o TCNT Internal overflow signal H'FF H'00 OVF Figure 10-5 Setting the OVF Bit 187 10.4 Usage Notes 10.4.1 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T3 state of a write cycle to the timer counter, the write takes priority and the timer counter is not incremented. See figure 10-6. Write cycle (CPU writes to TCNT) T1 o T2 T3 Internal address bus TCNT address Internal write signal TCNT clock pulse TCNT N M Counter write data Figure 10-6 TCNT Write-Increment Contention 10.4.2 Changing the Clock Select Bits (CKS2 to CKS0) Software should stop the watchdog timer (by clearing the TME bit to 0) before changing the value of the clock select bits. If the clock select bits are modified while the watchdog timer is running, the timer count may be incremented incorrectly. 10.4.3 Recovery from Software Standby Mode TCSR bits, except bits 0-2, and the TCNT counter are reset when the chip recovers from software standby mode. Re-initialize the watchdog timer as necessary to resume normal operation. 188 Section 11 Serial Communication Interface 11.1 Overview The H8/3297 Series includes a serial communication interface (SCI) for transferring serial data to and from other chips. Either synchronous or asynchronous communication can be selected. 11.1.1 Features The features of the on-chip serial communication interface are: * Asynchronous mode The H8/3297 Series can communicate with a UART (Universal Asynchronous Receiver/Transmitter), ACIA (Asynchronous Communication Interface Adapter), or other chip that employs standard asynchronous serial communication. It also has a multiprocessor communication function for communication with other processors. Twelve data formats are available. -- -- -- -- -- -- * Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Multiprocessor bit: 1 or 0 Error detection: Parity, overrun, and framing errors Break detection: When a framing error occurs, the break condition can be detected by reading the level of the RxD line directly. Synchronous mode The SCI can communicate with chips able to perform clocked synchronous data transfer. -- Data length: 8 bits -- Error detection: Overrun errors * Full duplex communication The transmitting and receiving sections are independent, so each channel can transmit and receive simultaneously. Both the transmit and receive sections use double buffering, so continuous data transfer is possible in either direction. * Built-in baud rate generator Any specified baud rate can be generated. * Internal or external clock source The SCI can operate on an internal clock signal from the baud rate generator, or an external clock signal input at the SCK pin. * Four interrupts TDR-empty, TSR-empty, receive-end, and receive-error interrupts are requested independently. 189 11.1.2 Block Diagram Figure 11-1 shows a block diagram of the serial communication interface. Bus interface BRR Baud rate generator Clock Internal data bus Module data bus RDR TDR SSR SCR SMR RxD RSR TSR Communication control Parity generate Parity check TxD Internal clock o oP/4 oP/16 oP/64 SCK External clock source TEI TXI RXI ERI Interrupt signals RSR: RDR: TSR: TDR: SMR: SCR: SSR: BRR: Receive shift register (8 bits) Receive data register (8 bits) Transmit shift register (8 bits) Transmit data register (8 bits) Serial mode register (8 bits) Serial control register (8 bits) Serial status register (8 bits) Bit rate register (8 bits) Figure 11-1 Block Diagram of Serial Communication Interface 190 11.1.3 Input and Output Pins Table 11-1 lists the input and output pins used by the SCI module. Table 11-1 SCI Input/Output Pins Name Serial clock input/output Receive data input Transmit data output Abbr. SCK RxD TxD I/O Input/output Input Output Function SCI clock input and output SCI receive data inp SCI transmit data output 11.1.4 Register Configuration Table 11-2 lists the SCI registers. These registers specify the operating mode (synchronous or asynchronous), data format and bit rate, and control the transmit and receive sections. Table 11-2 SCI Registers Name Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Serial/timer control register Abbr. RSR RDR TSR TDR SMR SCR SSR BRR STCR R/W -- R -- R/W R/W R/W R/(W)* R/W R/W Value -- H'00 -- H'FF H'00 H'00 H'84 H'FF H'F8 Addres -- H'FFDD -- H'FFDB H'FFD8 H'FFDA H'FFDC H'FFD9 H'FFC3 Note: * Software can write a 0 to clear the flags in bits 7 to 3, but cannot write 1 in these bits. 191 11.2 Register Descriptions 11.2.1 Receive Shift Register (RSR) Bit Read/Write 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- RSR is a shift register that converts incoming serial data to parallel data. When one data character has been received, it is transferred to the receive data register (RDR). The CPU cannot read or write RSR directly. 11.2.2 Receive Data Register (RDR) Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R RDR stores received data. As each character is received, it is transferred from RSR to RDR, enabling RSR to receive the next character. This double-buffering allows the SCI to receive data continuously. RDR is a read-only register. RDR is initialized to H'00 at a reset and in the standby modes. 11.2.3 Transmit Shift Register (TSR) Bit Read/Write 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- TSR is a shift register that converts parallel data to serial transmit data. When transmission of one character is completed, the next character is moved from the transmit data register (TDR) to TSR and transmission of that character begins. If the TDRE bit is still set to 1, however, nothing is transferred to TSR. The CPU cannot read or write TSR directly. 192 11.2.4 Transmit Data Register (TDR) Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W TDR is an 8-bit readable/writable register that holds the next data to be transmitted. When TSR becomes empty, the data written in TDR is transferred to TSR. Continuous data transmission is possible by writing the next data in TDR while the current data is being transmitted from TSR. TDR is initialized to H'FF at a reset and in the standby modes. 11.2.5 Serial Mode Register (SMR) Bit Initial value Read/Write 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SMR is an 8-bit readable/writable register that controls the communication format and selects the clock source of the on-chip baud rate generator. It is initialized to H'00 at a reset and in the standby modes. For further information on the SMR settings and communication formats, see tables 11-5 and 11-7 in section 11.3, Operation. Bit 7--Communication Mode (C/A): This bit selects asynchronous or synchronous communication mode. Bit 7 C/A 0 1 Description Asynchronous communication Synchronous communication (Initial value) 193 Bit 6--Character Length (CHR): This bit selects the character length in asynchronous mode. It is ignored in synchronous mode. Bit 6 CHR 0 1 Description 8 bits per character (Initial value) 7 bits per character (Bits 0 to 6 of TDR and RDR are used for transmitting and receiving, respectively.) Bit 5--Parity Enable (PE): This bit selects whether to add a parity bit in asynchronous mode. It is ignored in synchronous mode, and when a multiprocessor format is used. Bit 5 PE 0 Description Transmit: No parity bit is added. Receive: Parity is not checked. 1 Transmit: A parity bit is added. Receive: Parity is checked. (Initial value) Bit 4--Parity Mode (O/E ): In asynchronous mode, when parity is enabled (PE = 1), this bit selects even or odd parity. Even parity means that a parity bit is added to the data bits for each character to make the total number of 1's even. Odd parity means that the total number of 1's is made odd. This bit is ignored when PE = 0, or when a multiprocessor format is used. It is also ignored in synchronous mode. Bit 4 O/E 0 1 Description Even parity Odd parity (Initial value) 194 Bit 3--Stop Bit Length (STOP): This bit selects the number of stop bits. It is ignored in synchronous mode. Bit 3 STOP 0 Description One stop bit Transmit: One stop bit is added. Receive: One stop bit is checked to detect framing errors. (Initial value) 1 Two stop bits Transmit: Two stop bits are added. Receive: The first stop bit is checked to detect framing errors. If the second stop bit is a space (0), it is regarded as the next start bit. Bit 2--Multiprocessor Mode (MP): This bit selects the multiprocessor format in asynchronous communication. When multiprocessor format is selected, the parity settings of the parity enable bit (PE) and parity mode bit (O/E) are ignored. The MP bit is ignored in synchronous communication. The MP bit is valid only when the MPE bit in the serial/timer control register (STCR) is set to 1. When the MPE bit is cleared to 0, the multiprocessor communication function is disabled regardless of the setting of the MP bit. Bit 2 MP 0 1 Description Multiprocessor communication function is disabled. Multiprocessor communication function is enabled. (Initial value) Bits 1 and 0--Clock Select 1 and 0 (CKS1 and CKS0): These bits select the clock source of the on-chip baud rate generator. Bit 1 CKS1 0 0 1 1 Bit 0 CKS0 0 1 0 1 Description o clock oP/4 clock oP/16 clock oP/64 clock (Initial value) 195 11.2.6 Serial Control Register (SCR) Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W SCR is an 8-bit readable/writable register that enables or disables various SCI functions. It is initialized to H'00 at a reset and in the standby modes. Bit 7--Transmit Interrupt Enable (TIE): This bit enables or disables the TDR-empty interrupt (TXI) requested when the transmit data register empty (TDRE) bit in the serial status register (SSR) is set to 1. Bit 7 TIE 0 1 Description The TDR-empty interrupt request (TxI) is disabled. The TDR-empty interrupt request (TxI) is enabled. (Initial value) Bit 6--Receive Interrupt Enable (RIE): This bit enables or disables the receive-end interrupt (RXI) requested when the receive data register full (RDRF) bit in the serial status register (SSR) is set to 1, and the receive error interrupt (ERI) requested when the overrun error (ORER), framing error (FER), or parity error (PER) bit in the serial status register (SSR) is set to 1. Bit 6 RIE 0 1 Description The receive-end interrupt (RXI) and receive-error (ERI) requests are disabled. (Initial value) The receive-end interrupt (RXI) and receive-error (ERI) requests are enabled. Bit 5--Transmit Enable (TE): This bit enables or disables the transmit function. When the transmit function is enabled, the TxD pin is automatically used for output. When the transmit function is disabled, the TxD pin can be used as a general-purpose I/O port. Bit 5 TE 0 1 Description The transmit function is disabled. The TxD pin can be used for general-purpose I/O. The transmit function is enabled. The TxD pin is used for output. (Initial value) 196 Bit 4--Receive Enable (RE): This bit enables or disables the receive function. When the receive function is enabled, the RxD pin is automatically used for input. When the receive function is disabled, the RxD pin is available as a general-purpose I/O port. Bit 4 RE 0 1 Description The receive function is disabled. The RxD pin can be used for general-purpose I/O. The receive function is enabled. The RxD pin is used for input. (Initial value) Bit 3--Multiprocessor Interrupt Enable (MPIE): When serial data is received in a multiprocessor format, this bit enables or disables the receive-end interrupt (RXI) and receive-error interrupt (ERI) until data with the multiprocessor bit set to 1 is received. It also enables or disables the transfer of received data from RSR to RDR, and enables or disables setting of the RDRF, FER, PER, and ORER bits in the serial status register (SSR). The MPIE bit is ignored when the MP bit is cleared to 0, and in synchronous mode. Clearing the MPIE bit to 0 disables the multiprocessor receive interrupt function. In this condition data is received regardless of the value of the multiprocessor bit in the receive data. Setting the MPIE bit to 1 enables the multiprocessor receive interrupt function. In this condition, if the multiprocessor bit in the receive data is 0, the receive-end interrupt (RXI) and receive-error interrupt (ERI) are disabled, the receive data is not transferred from RSR to RDR, and the RDRF, FER, PER, and ORER bits in the serial status register (SSR) are not set. If the multiprocessor bit is 1, however, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0, the receive data is transferred from RSR to RDR, the FER, PER, and ORER bits can be set, and the receive-end and receive-error interrupts are enabled. Bit 3 MPIE 0 1 Description The multiprocessor receive interrupt function is disabled. (Normal receive operation) (Initial value) The multiprocessor receive interrupt function is enabled. During the interval before data with the multiprocessor bit set to 1 is received, the receive interrupt request (RxI) and receive-error interrupt request (ERI) are disabled, the RDRF, FER, PER, and ORER bits are not set in the serial status register (SSR), and no data is transferred from the RSR to the RDR. The MPIE bit is cleared at the following times: (1) When 0 is written in MPIE. (2) When data with the multiprocessor bit set to 1 is received. 197 Bit 2--Transmit-End Interrupt Enable (TEIE): This bit enables or disables the TSR-empty interrupt (TEI) requested when the transmit-end bit (TEND) in the serial status register (SSR) is set to 1. Bit 2 TEIE 0 1 Description The TSR-empty interrupt request (TEI) is disabled. The TSR-empty interrupt request (TEI) is enabled. (Initial value) Bit 1--Clock Enable 1 (CKE1): This bit selects the internal or external clock source for the baud rate generator. When the external clock source is selected, the SCK pin is automatically used for input of the external clock signal. Bit 1 CKE1 0 Description Internal clock source When C/A = 1, the serial clock signal is output at the SCK pin. When C/A = 0, output depends on the CKE0 bit. External clock source. The SCK pin is used for input. (Initial value) 1 Bit 0--Clock Enable 0 (CKE0): When an internal clock source is used in asynchronous mode, this bit enables or disables serial clock output at the SCK pin. This bit is ignored when the external clock is selected, or when synchronous mode is selected. For further information on the communication format and clock source selection, see table 11-6 in section 11.3, Operation. Bit 0 CKE0 0 1 Description The SCK pin is not used by the SCI (and is available as a general-purpose I/O port). The SCK pin is used for serial clock output. (Initial value) 198 11.2.7 Serial Status Register (SSR) Bit Initial value Read/Write 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Note: * Software can write a 0 to clear the flags, but cannot write a 1 in these bits. SSR is an 8-bit register that indicates transmit and receive status. It is initialized to H'84 at a reset and in the standby modes. Bit 7--Transmit Data Register Empty (TDRE): This bit indicates when transmit data can safely be written in TDR. Bit 7 TDRE 0 1 Description To clear TDRE, the CPU must read TDRE after it has been set to 1, then write a 0 in this bit. This bit is set to 1 at the following times: (1) When TDR contents are transferred to TSR. (2) When the TE bit in SCR is cleared to 0. (Initial value) Bit 6--Receive Data Register Full (RDRF): This bit indicates when one character has been received and transferred to the RDR. Bit 6 RDRF 0 1 Description To clear RDRF, the CPU must read RDRF after it has been set to 1, then write a 0 in this bit. This bit is set to 1 when one character is received without error and transferred from RSR to RDR. (Initial value) 199 Bit 5--Overrun Error (ORER): This bit indicates an overrun error during reception. Bit 5 ORER 0 1 Description To clear ORER, the CPU must read ORER after it has been set to 1, then write a 0 in this bit. This bit is set to 1 if reception of the next character ends while the receive data register is still full (RDRF = 1). (Initial value) Bit 4--Framing Error (FER): This bit indicates a framing error during data reception in asynchronous mode. It has no meaning in synchronous mode. Bit 4 FER 0 1 Description To clear FER, the CPU must read FER after it has been set to 1, then write a 0 in this bit. This bit is set to 1 if a framing error occurs (stop bit = 0). (Initial value) Bit 3--Parity Error (PER): This bit indicates a parity error during data reception in the asynchronous mode, when a communication format with parity bits is used. This bit has no meaning in the synchronous mode, or when a communication format without parity bits is used. Bit 3 PER 0 1 Description To clear PER, the CPU must read PER after it has been set to 1, then write a 0 in this bit. (Initial value) This bit is set to 1 when a parity error occurs (the parity of the received data does not match the parity selected by the O/E bit in SMR). 200 Bit 2--Transmit End (TEND): This bit indicates that the serial communication interface has stopped transmitting because there was no valid data in the TDR when the last bit of the current character was transmitted. The TEND bit is also set to 1 when the TE bit in the serial control register (SCR) is cleared to 0. The TEND bit is a read-only bit and cannot be modified directly. To use the TEI interrupt, first start transmitting data, which clears TEND to 0, then set TEIE to 1. Bit 2 TEND 0 1 Description To clear TEND, the CPU must read TDRE after TDRE has been set to 1, then write a 0 in TDRE This bit is set to 1 when: (1) TE = 0 (2) TDRE = 1 at the end of transmission of a character (Initial value) Bit 1--Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in data received in a multiprocessor format in asynchronous communication mode. This bit retains its previous value in synchronous mode, when a multiprocessor format is not used, or when the RE bit is cleared to 0 even if a multiprocessor format is used. MPB can be read but not written. Bit 1 MPB 0 1 Description Multiprocessor bit = 0 in receive data. Multiprocessor bit = 1 in receive data. (Initial value) Bit 0--Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit inserted in transmit data when a multiprocessor format is used in asynchronous communication mode. The MPBT bit is double-buffered in the same way as TSR and TDR. The MPBT bit has no effect in synchronous mode, or when a multiprocessor format is not used. Bit 0 MPBT 0 1 Description Multiprocessor bit = 0 in transmit data. Multiprocessor bit = 1 in transmit data. (Initial value) 201 11.2.8 Bit Rate Register (BRR) Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in SMR, determines the baud rate output by the baud rate generator. BRR is initialized to H'FF by a reset and in the standby modes. Tables 11-3 and 11-4 show examples of BRR settings. Table 11-3 Examples of BRR Settings in Asynchronous Mode (When oP = o) o Frequency (MHz) 2 Bit Rate 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 -- -- 0 -- N 141 103 207 103 51 25 12 -- -- 1 -- Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 -- -- 0 -- n 1 1 0 0 0 0 0 0 -- -- -- N 148 108 217 108 54 26 13 6 -- -- -- 2.097152 Error (%) -0.04 +0.21 +0.21 +0.21 -0.70 +1.14 -2.48 -2.48 -- -- -- Note: If possible, the error should be within 1%. 202 Table 11-3 Examples of BRR Settings in Asynchronous Mode (When oP = o) (cont) o Frequency (MHz) 2.4576 Bit Rate 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 0 0 -- 0 N 174 127 255 127 63 31 15 7 3 -- 1 Error (%) -0.26 0 0 0 0 0 0 0 0 -- 0 n 2 1 1 0 0 0 0 0 0 0 -- N 52 155 77 155 77 38 19 9 4 2 -- 3 Error (%) +0.50 +0.16 +0.16 +0.16 +0.16 +0.16 -2.34 -2.34 -2.34 0 -- n 2 1 1 0 0 0 0 0 0 -- 0 3.6864 N 64 191 95 191 95 47 23 11 5 -- 2 Error (%) +0.70 0 0 0 0 0 0 0 0 -- 0 n 2 1 1 0 0 0 0 0 -- 0 -- N 70 207 103 207 103 51 25 12 -- 3 -- 4 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 -- 0 -- Table 11-3 Examples of BRR Settings in Asynchronous Mode (When oP = o) (cont) o Frequency (MHz) 4.9152 Bit Rate 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) +0.31 0 0 0 0 0 0 0 0 -1.70 0 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) -0.25 +0.16 +0.16 +0.16 +0.16 +0.16 -1.36 +1.73 +1.73 0 +1.73 n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 6 Error (%) -0.44 0 0 0 +0.16 +0.16 +0.16 -2.34 -2.34 0 -2.34 n 2 2 1 1 0 0 0 0 0 0 0 6.144 N 108 79 159 79 159 79 39 19 4 5 4 Error (%) +0.08 0 0 0 0 0 0 0 0 +2.40 0 Note: If possible, the error should be within 1%. 203 Table 11-3 Examples of BRR Settings in Asynchronous Mode (When oP = o) (cont) o Frequency (MHz) 7.3728 Bit Rate 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 -- 0 N 130 95 191 95 191 95 47 23 11 -- 5 Error (%) -0.07 0 0 0 0 0 0 0 0 -- 0 n 2 2 1 1 0 0 0 0 0 0 -- N 141 103 207 103 207 103 51 25 12 7 -- 8 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 0 -- n 2 2 1 1 0 0 0 0 0 0 0 9.8304 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0 0 0 0 0 0 0 0 -1.70 0 n 3 2 2 1 1 0 0 0 0 0 0 N 43 129 64 129 64 129 64 32 15 9 7 10 Error (%) +0.88 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 -1.36 +1.73 0 +1.73 Table 11-3 Examples of BRR Settings in Asynchronous Mode (When oP = o) (cont) o Frequency (MHz) 12 Bit Rate 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 -2.34 0 -2.34 n 2 2 2 1 1 0 0 0 0 0 0 12.288 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) +0.08 0 0 0 0 0 0 0 0 +2.4 0 n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) +0.76 0 0 0 0 0 0 0 0 -1.7 0 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 0 +0.16 Note: If possible, the error should be within 1%. 204 B = F x 106/[64 x 22n-1 x (N + 1)] N = F x 106/[64 x 22n-1 x B] - 1 B: N: F: n: Baud rate (bits/second) BRR value (0 N 255) oP (MHz) when n 0, or o (MHz) when n = 0 Internal clock source (0, 1, 2, or 3) The meaning of n is given by the table below: n 0 1 2 3 CKS1 0 0 1 1 CKS0 0 1 0 1 Clock o oP/4 oP/16 oP/64 Bit rate error can be calculated with the formula below. Error (%) = { (N + 1) xFBx x10 x 2 64 6 2n-1 - 1 x 100 } 205 Table 11-4 Examples of BRR Settings in Synchronous Mode (When oP = o) o Frequency (MHz) 2 Bit Rate 100 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2.5 M 4M Blank: No setting is available. --: A setting is available, but the bit rate is inaccurate. *: Continuous transfer is not possible. n -- 2 1 1 0 0 0 0 0 0 0 0 N -- 124 249 124 199 99 49 19 9 4 1 0* n -- 2 2 1 1 0 0 0 0 0 0 0 0 4 N -- 249 124 249 99 199 99 39 19 9 3 1 0* n -- -- -- -- 1 0 0 0 0 -- 0 -- -- 5 N -- -- -- -- 124 249 124 49 24 -- 4 -- -- n -- 3 2 2 1 1 0 0 0 0 0 0 0 8 N -- 124 249 124 199 99 199 79 39 19 7 3 1 n -- -- -- -- 1 1 0 0 0 0 0 0 -- 0 10 N -- -- -- -- 249 124 249 99 49 24 9 4 -- 0* n -- 3 3 2 2 1 1 0 0 0 0 0 0 -- 0 16 N -- 249 124 249 99 199 99 159 79 39 15 7 3 -- 0* B = F x 106/[8 x 22n x (N + 1)] N = F x 106/[8 x 22n-1 x B] - 1 B: N: F: n: Baud rate (bits per second) BRR value (0 N 255) oP (MHz) when n 0, or o (MHz) when n = 0 Internal clock source (0, 1, 2, or 3) The meaning of n is given by the table below: n 0 1 2 3 CKS1 0 0 1 1 CKS0 0 1 0 1 Clock o oP/4 oP/16 oP/64 206 11.2.9 Serial/Timer Control Register (STCR) Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 MPE 0 R/W 1 ICKS1 0 R/W 0 ICKS0 0 R/W STCR is an 8-bit readable/writable register that controls the SCI operating mode and selects the TCNT clock source in the 8-bit timers. STCR is initialized to H'F8 by a reset. Bits 7 to 3--Reserved: These bits cannot be modified, and are always read as 1. Bit 2--Multiprocessor Enable (MPE): Enables or disables the multiprocessor communication function on channels SCI0 and SCI1. Bit 2 MPE 0 1 Description The multiprocessor communication function is disabled, regardless of the setting of the MP bit in SMR. (Initial value) The multiprocessor communication function is enabled. The multi-processor format can be selected by setting the MP bit in SMR to 1. Bits 1 and 0--Internal Clock Source Select 1 and 0 (ICKS1, ICKS0): These bits select the clock input to the timer counters (TCNT) in the 8-bit timers. For details, see section 9, 8-Bit Timers. 207 11.3 Operation 11.3.1 Overview The SCI supports serial data transfer in two modes. In asynchronous mode each character is synchronized individually. In synchronous mode communication is synchronized with a clock signal. The selection of asynchronous or synchronous mode and the communication format depend on SMR settings as indicated in table 11-5. The clock source depends on the settings of the C/A bit in the SMR and the CKE1 and CKE0 bits in SCR as indicated in table 11-6. Asynchronous Mode * * Data length: 7 or 8 bits can be selected. A parity bit or multiprocessor bit can be added, and stop bit lengths of 1 or 2 bits can be selected. (These selections determine the communication format and character length.) Framing errors (FER), parity errors (PER), and overrun errors (ORER) can be detected in receive data, and the line-break condition can be detected. SCI clock source: an internal or external clock source can be selected. Internal clock: The SCI is clocked by the on-chip baud rate generator and can output a clock signal at the bit-rate frequency. External clock: The external clock frequency must be 16 times the bit rate. (The on-chip baud rate generator is not used.) * * * * Synchronous Mode * * * * Communication format: The data length is 8 bits. Overrun errors (ORER) can be detected in receive data. SCI clock source: an internal or external clock source can be selected. Internal clock: The SCI is clocked by the on-chip baud rate generator and outputs a serial clock signal to external devices. External clock: The on-chip baud rate generator is not used. The SCI operates on the input serial clock. * 208 Table 11-5 Communication Formats Used by SCI SMR Settings Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 C/A CHR MP PE STOP Mode 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 -- 0 1 1 0 1 1 -- -- -- -- Synchronous mode 8 bits None Asynchronous mode (multiprocessor format) 8 bits Present None Present 7 bits None Asynchronous mode Data Length 8 bits Communication Format Multiprocessor Bit None Parity Bit None StopBit Length 1 bit 2 bits Present 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 7 bits 1 bit 2 bits None Table 11-6 SCI Clock Source Selection SMR SCR Serial Transmit/Receive Clock Mode Async Clock Source Internal SCK Pin Function Input/output port (not used by SCI) Serial clock output at bit rate External Serial clock input at 16 x bit rate Bit 7 Bit 1 Bit 0 C/A CKE1 CKE0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Sync Internal Serial clock output External Serial clock input 209 11.3.2 Asynchronous Mode In asynchronous mode, each transmitted or received character is individually synchronized by framing it with a start bit and stop bit. Full duplex data transfer is possible because the SCI has independent transmit and receive sections. Double buffering in both sections enables the SCI to be programmed for continuous data transfer. Figure 11-2 shows the general format of one character sent or received in asynchronous mode. The communication channel is normally held in the mark state (high). Character transmission or reception starts with a transition to the space state (low). The first bit transmitted or received is the start bit (low). It is followed by the data bits, in which the least significant bit (LSB) comes first. The data bits are followed by the parity or multiprocessor bit, if present, then the stop bit or bits (high) confirming the end of the frame. In receiving, the SCI synchronizes on the falling edge of the start bit, and samples each bit at the center of the bit (at the 8th cycle of the internal serial clock, which runs at 16 times the bit rate). Idle state (mark) "1" "0" (LSB) D1 D2 D3 D4 D5 D6 (MSB) D7 0/1 "1" "1" "1" Start bit Transmit/receive data 1 bit 7 or 8 bits Parity bit Stop bit 1 bit or no bit 1 or 2 bits One unit of data (one character or frame) Figure 11-2 Data Format in Asynchronous Mode (Example of 8-Bit Data with Parity Bit and Two Stop Bits) 210 (1) Data Format: Table 11-7 lists the data formats that can be sent and received in asynchronous mode. Twelve formats can be selected by bits in the serial mode register (SMR). Table 11-7 Data Formats in Asynchronous Mode SMR Bits CHR PE 0 0 0 0 1 1 1 1 0 0 1 1 Notes: 0 0 1 1 0 0 1 1 -- -- -- -- MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 S S S S S S S S S S S S 2 3 4 5 6 7 8 9 10 STOP STOP STOP P P STOP STOP STOP P P STOP STOP STOP MPB STOP MPB STOP STOP MPB STOP MPB STOP STOP STOP STOP STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data SMR: Serial mode register S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit (2) Clock: In asynchronous mode it is possible to select either an internal clock created by the onchip baud rate generator, or an external clock input at the SCK pin. The selection is made by the C/A bit in the serial mode register (SMR) and the CKE1 and CKE0 bits in the serial control register (SCR). Refer to table 11-6. If an external clock is input at the SCK pin, its frequency should be 16 times the desired bit rate. If the internal clock provided by the on-chip baud rate generator is selected and the SCK pin is used for clock output, the output clock frequency is equal to the bit rate, and the clock pulse rises at the center of the transmit data bits. Figure 11-3 shows the phase relationship between the output clock and transmit data. 211 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 One frame Figure 11-3 Phase Relationship between Clock Output and Transmit Data (Asynchronous Mode) (3) Transmitting and Receiving Data * SCI Initialization: Before transmitting or receiving, software must clear the TE and RE bits to 0 in the serial control register (SCR), then initialize the SCI following the procedure in figure 11-4. Note: When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which retain their previous contents. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCI operation becomes unreliable if the clock is stopped. 212 Initialization 1. Clear TE and RE bits to 0 in SCR 2. 1 Set CKE1 and CKE0 bits in SCR (leaving TE and RE cleared to 0) Select interrupts and the clock source in the serial control register (SCR). Leave TE and RE cleared to 0. If clock output is selected, in asynchronous mode, clock output starts immediately after the setting is made in SCR. Select the communication format in the serial mode register (SMR). Write the value corresponding to the bit rate in the bit rate register (BRR). This step is not necessary when an external clock is used. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the serial control register (SCR). Setting TE or RE enables the SCI to use the TxD or RxD pin. Also set the RIE, TIE, TEIE, and MPIE bits as necessary to enable interrupts. The initial states are the mark transmit state, and the idle receive state (waiting for a start bit). 3. 2 Select communication format in SMR 4. 3 Set value in BRR 1 bit interval elapsed? Yes 4 No Note: In simultaneous transmit/receive operations, the TE and RE bits should be set to 1 or cleared to 0 simultaneously. Set TE or RE to 1 in SCR, and set RIE, TIE, TEIE, and MPIE as necessary Start transmitting or receiving Figure 11-4 Sample Flowchart for SCI Initialization 213 * Transmitting Serial Data: Follow the procedure in figure 11-5 for transmitting serial data. 1 Initialize 1. SCI initialization: the transmit data output function of the TxD pin is selected automatically. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. If a multiprocessor format is selected, after writing the transmit data write 0 or 1 in the multiprocessor bit transfer (MPBT) in SSR. Transition of the TDRE bit from 0 to 1 can be reported by an interrupt. Start transmitting 2. 2 Read TDRE bit in SSR No TDRE = 1? Yes Write transmit data in TDR If using multiprocessor format, select MPBT value in SSR Clear TDRE bit to 0 Serial transmission End of transmission? Yes No 3. (a) To continue transmitting serial data: read the TDRE bit to check whether it is safe to write; if TDRE = 1, write data in TDR, then clear TDRE to 0. (b) To end serial transmission: end of transmission can be confirmed by checking transition of the TEND bit from 0 to 1. This can be reported by a TEI interrupt. 4. To output a break signal at the end of serial transmission: set the DDR bit to 1 and clear the DR bit to 0 (DDR and DR are I/O port registers), then clear TE to 0 in SCR. 3 Read TEND bit in SSR No TEND = 1? Yes Output break signal? Yes Set DR = 0, DDR = 1 Clear TE bit in SCR to 0 4 No End Figure 11-5 Sample Flowchart for Transmitting Serial Data 214 In transmitting serial data, the SCI operates as follows. 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR). After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the TIE bit (TDR-empty interrupt enable) is set to 1 in SCR, the SCI requests a TXI interrupt (TDR-empty interrupt) at this time. Serial transmit data are transmitted in the following order from the TxD pin: (a) Start bit: one 0 bit is output. (b) Transmit data: seven or eight bits are output, LSB first. (c) Parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. (d) Stop bit: one or two 1 bits (stop bits) are output. (e) Mark state: output of 1 bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, after loading new data from TDR into TSR and transmitting the stop bit, the SCI begins serial transmission of the next frame. If TDRE is 1, after setting the TEND bit to 1 in SSR and transmitting the stop bit, the SCI continues 1-level output in the mark state, and if the TEIE bit (TSR-empty interrupt enable) in SCR is set to 1, the SCI generates a TEI interrupt request (TSR-empty interrupt). 2. 215 Figure 11-6 shows an example of SCI transmit operation in asynchronous mode. 1 Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 Mark (idle) state TDRE TEND TXI TXI interrupt handler request writes data in TDR and clears TDRE to 0 1 frame TXI request TEI request Figure 11-6 Example of SCI Transmit Operation (8-Bit Data with Parity and One Stop Bit) 216 * Receiving Serial Data: Follow the procedure in figure 11-7 for receiving serial data. 1 Initialize 1. SCI initialization: the receive data function of the RxD pin is selected automatically. 2. To continue receiving serial data: read RDR and clear RDRF to 0 before the stop bit of the current frame is received. 3. SCI status check and receive data read: read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. Transition of the RDRF bit from 0 to 1 can be reported by an RXI interrupt. 4 Error handling No 4. Receive error handling and break detection: if a receive error occurs, read the ORER, PER, and FER bits in SSR to identify the error. After executing the necessary error handling, clear ORER, PER, and FER all to 0. Transmitting and receiving cannot resume if ORER, PER, or FER remains set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. Start receiving 2 Read ORER, PER, and FER in SSR PER RER ORER = 1? No Yes 3 Read RDRF bit in SSR RDRF = 1? Yes Read receive data from RDR, and clear RDRF bit to 0 in SSR Finished receiving? Yes Clear RE to 0 in SCR No End Start error handling FER = 1? No Discriminate and process error, and clear flags Return Yes Break? No Yes Clear RE to 0 in SCR End Figure 11-7 Sample Flowchart for Receiving Serial Data 217 In receiving, the SCI operates as follows. 1. 2. 3. The SCI monitors the receive data line and synchronizes internally when it detects a start bit. Receive data is shifted into RSR in order from LSB to MSB. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following checks: (a) Parity check: the number of 1s in the receive data must match the even or odd parity setting of the O/E bit in SMR. (b) Stop bit check: the stop bit value must be 1. If there are two stop bits, only the first stop bit is checked. (c) Status check: RDRF must be 0 so that receive data can be loaded from RSR into RDR. If these checks all pass, the SCI sets RDRF to 1 and stores the received data in RDR. If one of the checks fails (receive error), the SCI operates as indicated in table 11-8. Note: When a receive error flag is set, further receiving is disabled. The RDRF bit is not set to 1. Be sure to clear the error flags. 4. After setting RDRF to 1, if the RIE bit (receive-end interrupt enable) is set to 1 in SCR, the SCI requests an RXI (receive-end) interrupt. If one of the error flags (ORER, PER, or FER) is set to 1 and the RIE bit in SCR is also set to 1, the SCI requests an ERI (receive-error) interrupt. 218 Figure 11-8 shows an example of SCI receive operation in asynchronous mode. Table 11-8 Receive Error Conditions and SCI Operation Receive error Overrun error Abbreviation ORER Condition Receiving of next data ends while RDRF is still set to 1 in SSR Stop bit is 0 Parity of receive data differs from even/odd parity setting in SMR Data Transfer Receive data not loaded from RSR into RDR Receive data loaded from RSR into RDR Receive data loaded from RSR into RDR Framing error Parity error FER PER 1 Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 1 Mark (idle) state RDRF FER RXI request 1 frame RXI interrupt handler reads data in RDR and clears RDRF to 0 Framing error, ERI request Figure 11-8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit) 219 (4) Multiprocessor Communication The multiprocessor communication function enables several processors to share a single serial communication line. The processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by an ID. A serial communication cycle consists of two cycles: an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending cycles. The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. After receiving data with the multiprocessor bit set to 1, the receiving processor with an ID matching the received data continues to receive further incoming data. Multiple processors can send and receive data in this way. Four formats are available. Parity-bit settings are ignored when a multiprocessor format is selected. For details see table 11-7. 220 Transmitting processor Serial communication line Receiving processor A (ID = 01) Receiving processor B (ID = 02) Receiving processor C (ID = 03) Receiving processor D (ID = 04) Serial data H'01 (MPB = 1) ID-sending cycle: receiving processor address H'AA (MPB = 0) Data-sending cycle: data sent to receiving processor specified by ID MPB: multiprocessor bit Figure 11-9 Example of Communication among Processors using Multiprocessor Format (Sending Data H'AA to Receiving Processor A) 221 * Transmitting Multiprocessor Serial Data: See figures 11-5 and 11-6. * Receiving Multiprocessor Serial Data: Follow the procedure in figure 11-10 for receiving multiprocessor serial data. 1 Initialize 1. SCI initialization: the receive data function of the RxD pin is selected automatically. ID receive cycle: Set the MPIE bit in the serial control register (SCR) to 1. SCI status check and ID check: read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and compare with the processor's own ID. Transition of the RDRF bit from 0 to 1 can be reported by an RXI interrupt. If the ID does not match the receive data, set MPIE to 1 again and clear RDRF to 0. If the ID matches the receive data, clear RDRF to 0. SCI status check and data receiving: read SSR, check that RDRF is set to 1, then read data from the receive data register (RDR) and write 0 in the RDRF bit. Transition of the RDRF bit from 0 to 1 can be reported by an RXI interrupt. Receive error handling and break detection: if a receive error occurs, read the ORER and FER bits in SSR to identify the error. After executing the necessary error handling, clear both ORER and FER to 0. Receiving cannot resume while ORER or FER remains set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. Start receiving 2. 2 Set MPIE bit to 1 in SCR 3. Read ORER and FER bits in SSR FER ORER = 1? No 3 Read RDRF bit in SSR 5. No RDRF = 1? Yes Read receive data from RDR No Yes 4. Own ID? Yes Read ORER and FER bits in SSR FER + ORER = 1? No 4 Read RDRF bit in SSR Yes RDRF = 1? Yes No Start error handling Read receive data from RDR 5 Error handling FER = 1? No Discriminate and process error, and clear flags Return Yes Break? No Yes Finished receiving? Yes Clear RE to 0 in SCR No Clear RE bit to 0 in SCR End End Figure 11-10 Sample Flowchart for Receiving Multiprocessor Serial Data 222 Figure 11-11 shows an example of an SCI receive operation using a multiprocessor format (8-bit data with multiprocessor bit and one stop bit). 1 Start bit 0 D0 Data (ID1) D1 D7 Stop Start MPB bit bit 1 1 0 Data (Data1) D0 D1 D7 Stop MPB bit 0 1 1 Mark (idle) state MPIE RDRF RDR value MPB detection (MPIE=0) RXI request RXI handler reads RDR data and clears RDRF to 0 ID1 Not own ID, so MPIE is set to 1 again No RXI request, RDR not updated (Multiprocessor interrupt) (a) Own ID does not match data 1 Start bit 0 D0 Data (ID2) D1 D7 Stop Start MPB bit bit 1 1 0 Data (Data2) D0 D1 D7 Stop MPB bit 0 1 1 Mark (idle) state MPIE RDRF RDR value MPB detection (MPIE=0) ID2 RXI request RXI handler reads Own ID, so receiving RDR data and clears continues, with data RDRF to 0 received at each RXI Data 2 MPIE set to 1 again (Multiprocessor interrupt) (b) Own ID matches data Figure 11-11 Example of SCI Receive Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit) 223 11.3.3 Synchronous Mode (1) Overview: In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so full duplex communication is possible. The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 11-12 shows the general format in synchronous serial communication. One unit (character or frame) of serial data * Serial clock LSB Serial data Don't care Note: * High except in continuous transmitting or receiving Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care * Figure 11-12 Data Format in Synchronous Communication In synchronous serial communication, each data bit is sent on the communication line from one falling edge of the serial clock to the next. Data is received in synchronization with the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from LSB (first) to MSB (last). After output of the MSB, the communication line remains in the state of the MSB. 224 * Communication Format: The data length is fixed at eight bits. No parity bit or multiprocessor bit can be added. * Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected by clearing or setting the CKE1 bit in the serial control register (SCR). See table 11-6. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains at the high level. (2) Transmitting and Receiving Data * SCI Initialization: The SCI must be initialized in the same way as in asynchronous mode. See figure 11-4. When switching from asynchronous mode to synchronous mode, check that the ORER, FER, and PER bits are cleared to 0. Transmitting and receiving cannot begin if ORER, FER, or PER is set to 1. 225 * Transmitting Serial Data: Follow the procedure in figure 11-13 for transmitting serial data. 1 Initialize 1. SCI initialization: the transmit data output function of the TxD pin is selected automatically. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. Transition of the TDRE bit from 0 to 1 can be reported by a TXI interrupt. Start transmitting 2. 2 Read TDRE bit in SSR No TDRE = 1? Yes Write transmit data in TDR and clear TDRE bit to 0 in SSR Serial transmission End of transmission? Yes No 3. (a) To continue transmitting serial data: read the TDRE bit to check whether it is safe to write; if TDRE = 1, write data in TDR, then clear TDRE to 0. (b) To end serial transmission: end of transmission can be confirmed by checking transition of the TEND bit from 0 to 1. This can be reported by a TEI interrupt. 3 Read TEND bit in SSR No TEND = 1? Yes Clear TE bit to 0 in SCR End Figure 11-13 Sample Flowchart for Serial Transmitting 226 In transmitting serial data, the SCI operates as follows. 1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI recognizes that the transmit data register (TDR) contains new data, and loads this data from TDR into the transmit shift register (TSR). After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the TIE bit (TDR-empty interrupt enable) in SCR is set to 1, the SCI requests a TXI interrupt (TDR-empty interrupt) at this time. If clock output is selected the SCI outputs eight serial clock pulses, triggered by the clearing of the TDRE bit to 0. If an external clock source is selected, the SCI outputs data in synchronization with the input clock. Data is output from the TxD pin in order from LSB (bit 0) to MSB (bit 7). 3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads data from TDR into TSR, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in SSR to 1, transmits the MSB, then holds the output in the MSB state. If the TEIE bit (transmit-end interrupt enable) in SCR is set to 1, a TEI interrupt (TSR-empty interrupt) is requested at this time. After the end of serial transmission, the SCK pin is held at the high level. 2. 4. 227 Figure 11-14 shows an example of SCI transmit operation. Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI request TXI interrupt TXI handler writes request data in TDR and clears TDRE to 0 1 frame TEI request Figure 11-14 Example of SCI Transmit Operation 228 * Receiving Serial Data: Follow the procedure in figure 11-15 for receiving serial data. When switching from asynchronous mode to synchronous mode, be sure to check that PER and FER are cleared to 0. If PER or FER is set to 1 the RDRF bit will not be set and both transmitting and receiving will be disabled. 1 Initialize 1. SCI initialization: the receive data function of the RxD pin is selected automatically. Receive error handling: if a receive error occurs, read the ORER bit in SSR then, after executing the necessary error handling, clear ORER to 0. Neither transmitting nor receiving can resume while ORER remains set to 1. When clock output mode is selected, receiving can be halted temporarily by receiving one dummy byte and causing an overrun error. When preparations to receive the next data are completed, clear the ORER bit to 0. This causes receiving to resume, so return to the step marked 2 in the flowchart. SCI status check and receive data read: read the serial status register (SSR), check that RDRF is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. Transition of the RDRF bit from 0 to 1 can be reported by an RXI interrupt. To continue receiving serial data: read RDR and clear RDRF to 0 before the MSB (bit 7) of the current frame is received. Start receiving 2. Read ORER bit in SSR Yes ORER = 1? No 3 Read RDRF in SSR 2 Error handling 3. RDRF = 1? Yes Read receive data from RDR, and clear RDRF bit to 0 in SSR No 4 4. Finished receiving? Yes Clear RE to 0 in SCR No End Start error handling Overrun error handling Clear ORER to 0 in SSR Return Figure 11-15 Sample Flowchart for Serial Receiving 229 In receiving, the SCI operates as follows. 1. If an external clock is selected, data is input in synchronization with the input clock. If clock output is selected, as soon as the RE bit is set to 1 the SCI begins outputting the serial clock and inputting data. If clock output is stopped because the ORER bit is set to 1, output of the serial clock and input of data resume as soon as the ORER bit is cleared to 0. Receive data is shifted into RSR in order from LSB to MSB. After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from RSR into RDR. If this check passes, the SCI sets RDRF to 1 and stores the received data in RDR. If the check does not pass (receive error), the SCI operates as indicated in table 11-8. Note: Both transmitting and receiving are disabled while a receive error flag is set. The RDRF bit is not set to 1. Be sure to clear the error flag. 3. After setting RDRF to 1, if the RIE bit (receive-end interrupt enable) is set to 1 in SCR, the SCI requests an RXI (receive-end) interrupt. If the ORER bit is set to 1 and the RIE bit in SCR is set to 1, the SCI requests an ERI (receive-error) interrupt. When clock output mode is selected, clock output stops when the RE bit is cleared to 0 or the ORER bit is set to 1. To prevent clock count errors, it is safest to receive one dummy byte and generate an overrun error. 2. 230 Figure 11-16 shows an example of SCI receive operation. Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI request RXI interrupt handler reads data in RDR and clears RDRF to 0 1 frame RXI request Overrun error, ERI request Figure 11-16 Example of SCI Receive Operation 231 * Transmitting and Receiving Serial Data Simultaneously: Follow the procedure in figure 11-17 for transmitting and receiving serial data simultaneously. If clock output mode is selected, output of the serial clock begins simultaneously with serial transmission. 1 Initialize 1. Start 2. 2 Read TDRE bit in SSR SCI initialization: the transmit data output function of the TxD pin and receive data input function of the RxD pin are selected, enabling simultaneous transmitting and receiving. SCI status check and transmit data write: read the serial status register (SSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (TDR) and clear TDRE to 0. Transition of the TDRE bit from 0 to 1 can be reported by a TXI interrupt. SCI status check and receive data read: read the serial status register (SSR), check that the RDRF bit is 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. Transition of the RDRF bit from 0 to 1 can be reported by an RXI interrupt. Receive error handling: if a receive error occurs, read the ORER bit in SSR then, after executing the necessary error handling, clear ORER to 0. Neither transmitting nor receiving can resume while ORER remains set to 1. No TDRE = 1? 3. Yes 3 Write transmit data in TDR and clear TDRE bit to 0 in SSR 4. Read ORER bit in SSR ORER = 1? No Read RDRF bit in SSR Yes 4 Error handling 5. No RDRF = 1? Yes Read receive data from RDR and clear RDRF bit to 0 in SSR To continue transmitting and receiving serial data: read RDR and clear RDRF to 0 before the MSB (bit 7) of the current frame is received. Also read the TDRE bit and check that it is set to 1, indicating that it is safe to write; then write data in TDR and clear TDRE to 0 before the MSB (bit 7) of the current frame is transmitted. 5 End of transmitting and receiving? Yes Clear TE and RE bits to 0 in SCR No End Figure 11-17 Sample Flowchart for Serial Transmitting and Receiving Note: In switching from transmitting or receiving to simultaneous transmitting and receiving, clear both TE and RE to 0, then set both TE and RE to 1 at the same time. 232 11.4 Interrupts The SCI can request four types of interrupts: ERI, RXI, TXI, and TEI. Table 11-9 indicates the source and priority of these interrupts. The interrupt sources can be enabled or disabled by the TIE, RIE, and TEIE bits in the SCR. Independent signals are sent to the interrupt controller for each interrupt source, except that the receive-error interrupt (ERI) is the logical OR of three sources: overrun error, framing error, and parity error. The TXI interrupt indicates that the next transmit data can be written. The TEI interrupt indicates that the SCI has stopped transmitting data. Table 11-9 SCI Interrupt Sources Interrupt ERI RxI TxI TEI Description Receive-error interrupt (ORER, FER, or PER) Receive-end interrupt (RDRF) TDR-empty interrupt (TDRE) TSR-empty interrupt (TEND) Low Priority High 11.5 Usage Notes Application programmers should note the following features of the SCI. (1) TDR Write: The TDRE bit in SSR is simply a flag that indicates that the TDR contents have been transferred to TSR. The TDR contents can be rewritten regardless of the TDRE value. If a new byte is written in TDR while the TDRE bit is 0, before the old TDR contents have been moved into TSR, the old byte will be lost. Software should check that the TDRE bit is set to 1 before writing to TDR. (2) Multiple Receive Errors: Table 11-10 lists the values of flag bits in the SSR when multiple receive errors occur, and indicates whether the RSR contents are transferred to RDR. 233 Table 11-10 SSR Bit States and Data Transfer when Multiple Receive Errors Occur SSR Bits Receive error Overrun error Framing error Parity error Overrun and framing errors Overrun and parity errors Framing and parity errors Overrun, framing, and parity errors RDRF 1*1 0 0 1*1 1*1 0 1*1 ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 RSR RDR*2 No Yes Yes No No Yes No Notes: 1. Set to 1 before the overrun error occurs. 2. Yes: The RSR contents are transferred to RDR. No: The RSR contents are not transferred to RDR. (3) Line Break Detection: When the RxD pin receives a continuous stream of 0's in asynchronous mode (line-break state), a framing error occurs because the SCI detects a 0 stop bit. The value H'00 is transferred from RSR to RDR. Software can detect the line-break state as a framing error accompanied by H'00 data in RDR. The SCI continues to receive data, so if the FER bit is cleared to 0 another framing error will occur. (4) Sampling Timing and Receive Margin in Asynchronous Mode: The serial clock used by the SCI in asynchronous mode runs at 16 times the baud rate. The falling edge of the start bit is detected by sampling the RxD input on the falling edge of this clock. After the start bit is detected, each bit of receive data in the frame (including the start bit, parity bit, and stop bit or bits) is sampled on the rising edge of the serial clock pulse at the center of the bit. See figure 11-18. It follows that the receive margin can be calculated as in equation (1). When the absolute frequency deviation of the clock signal is 0 and the clock duty cycle is 0.5, data can theoretically be received with distortion up to the margin given by equation (2). This is a theoretical limit, however. In practice, system designers should allow a margin of 20% to 30%. 234 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1516 1 2 3 4 5 6 7 8 9 10 11 12 1314 15 16 1 2 3 4 5 Basic clock -7.5 pulses Receive data Start bit +7.5 pulses D0 D1 Sync sampling Data sampling Figure 11-18 Sampling Timing (Asynchronous Mode) M = {(0.5 - 1/2N) - (D - 0.5)/N - (L - 0.5)F} x 100 [%] M: N: D: L: F: Receive margin Ratio of basic clock to baud rate (N=16) Duty factor of clock--ratio of high pulse width to low width (0.5 to 1.0) Frame length (9 to 12) Absolute clock frequency deviation (1) When D = 0.5 and F = 0 M = (0.5 -1/2 x 16) x 100 [%] = 46.875% (2) 235 Section 12 A/D Converter 12.1 Overview The H8/3297 includes a 10-bit successive-approximations A/D converter with a selection of up to eight analog input channels. 12.1.1 Features A/D converter features are listed below. * * * 10-bit resolution Eight input channels High-speed conversion Conversion time: minimum 8.4 s per channel (with 16-MHz system clock) * Two conversion modes Single mode: A/D conversion of one channel Scan mode: continuous conversion on one to four channels * Four 16-bit data registers A/D conversion results are transferred for storage into data registers corresponding to the channels. * * * Sample-and-hold function A/D conversion can be externally triggered A/D interrupt requested at end of conversion At the end of A/D conversion, an A/D end interrupt (ADI) can be requested. 237 12.1.2 Block Diagram Figure 12-1 shows a block diagram of the A/D converter. Module data bus Bus interface ADDRC ADDRD ADDRA ADDRB ADCSR + - Analog multiplexer Comparator Control circuit Sample-andhold circuit ADCR Internal data bus AVCC 10-bit D/A AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Successiveapproximations register oP/8 oP/16 ADTRG Legend ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: ADI interrupt signal A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D Figure 12-1 A/D Converter Block Diagram 238 12.1.3 Input Pins Table 12-1 lists the A/D converter's input pins. The eight analog input pins are divided into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). AVCC and AVSS are the power supply for the analog circuits in the A/D converter. Table 12-1 A/D Converter Pins Pin Name Analog power supply pin Analog ground pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin Abbreviation AVCC AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG I/O Input Input Input Input Input Input Input Input Input Input Input External trigger input for starting A/D conversion Group 1 analog inputs Function Analog power supply Analog ground and reference voltage Group 0 analog inputs 239 12.1.4 Register Configuration Table 12-2 summarizes the A/D converter's registers. Table 12-2 A/D Converter Registers Name A/D data register A (high) A/D data register A (low) A/D data register B (high) A/D data register B (low) A/D data register C (high) A/D data register C (low) A/D data register D (high) A/D data register D (low) A/D control/status register A/D control register Abbreviation ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR R/W R R R R R R R R R/W* R/W Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'7F Address H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 Note: * Only 0 can be written in bit 7, to clear the flag. 240 12.2 Register Descriptions 12.2.1 A/D Data Registers A to D (ADDRA to ADDRD) Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 6 5 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Bits 15 to 6--A/D Conversion Data (AD9 to AD0): 10-bit data giving an A/D conversion result. Bits 5 to 0--Reserved: These bits cannot be modified and are always read as 0. The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion. An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D data register are reserved bits that always read 0. Table 12-3 indicates the pairings of analog input channels and A/D data registers. The CPU can always read and write the A/D data registers. The upper byte can be read directly, but the lower byte is read through a temporary register (TEMP). For details see section 12.3, CPU Interface. The A/D data registers are initialized to H'0000 by a reset and in standby mode. Table 12-3 Analog Input Channels and A/D Data Registers Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD 241 12.2.2 A/D Control/Status Register (ADCSR) Bit Initial value Read/Write 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Note: * Only 0 can be written, to clear the flag. ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter. ADCSR is initialized to H'00 by a reset and in standby mode. Bit 7--A/D End Flag (ADF): Indicates the end of A/D conversion. Bit 7 ADF 0 1 Description [Clearing condition] Cleared by reading ADF while ADF = 1, then writing 0 in ADF [Setting conditions] 1. Single mode: A/D conversion ends 2. Scan mode: A/D conversion ends in all selected channels (Initial value) Bit 6--A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the end of A/D conversion. Bit 6 ADIE 0 1 Description A/D end interrupt request (ADI) is disabled A/D end interrupt request (ADI) is enabled (Initial value) Bit 5--A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin. Bit 5 ADST 0 1 Description A/D conversion is stopped (Initial value) 1. Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends 2. Scan mode: A/D conversion starts and continues, cycling among the selected channels, until ADST is cleared to 0 by software, by a reset, or by a transition to standby mode 242 Bit 4--Scan Mode (SCAN): Selects single mode or scan mode. For further information on operation in these modes, see section 12.4, Operation. Clear the ADST bit to 0 before switching the conversion mode. Bit 4 SCAN 0 1 Description Single mode Scan mode (Initial value) Bit 3--Clock Select (CKS): Selects the A/D conversion time. When oP = o/2, the conversion time doubles. Clear the ADST bit to 0 before switching the conversion time. Bit 3 CKS 0 1 Description Conversion time = 266 states (maximum) (when oP = o) Conversion time = 134 states (maximum) (when oP = o) (Initial value) Bits 2 to 0--Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog input channels. Clear the ADST bit to 0 before changing the channel selection. Group Selection CH2 0 Channel Selection CH1 0 0 1 1 1 0 0 1 1 CH0 0 1 0 1 0 1 0 1 Single Mode AN0 (initial value) AN1 AN2 AN3 AN4 AN5 AN6 AN7 Description Scan Mode AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 243 12.2.3 A/D Control Register (ADCR) Bit Initial value Read/Write 7 TRGE 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion. ADCR is initialized to H'7F by a reset and in standby mode. Bit 7--Trigger Enable (TRGE): Enables or disables external triggering of A/D conversion. Bit 7 TRGE 0 1 Description A/D conversion cannot be externally triggered (Initial value) Enables start of A/D conversion by the external trigger signal (ADTRG) (A/D conversion can be started either by an external trigger or by software.) Bits 6 to 0--Reserved: These bits cannot be modified, and are always read as 1. 244 12.3 CPU Interface ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus. Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is read through an 8-bit temporary register (TEMP). An A/D data register is read as follows. When the upper byte is read, the upper-byte value is transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading an A/D data register, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 12-2 shows the data flow for access to an A/D data register. Upper-byte read CPU (H'AA) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Lower-byte read CPU (H'40) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Figure 12-2 A/D Data Register Access Operation (Reading H'AA40) 245 12.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 12.4.1 Single Mode (SCAN = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when conversion ends. When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is requested at this time. To clear the ADF flag to 0, first read ADCSR, then write 0 in ADF. When the mode or analog input channel must be switched during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the mode or channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 12-3 shows a timing diagram for this example. 1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). When A/D conversion is completed, the result is transferred into ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. The A/D interrupt handling routine starts. The routine reads ADCSR, then writes 0 in the ADF flag. The routine reads and processes the conversion result (ADDRB). Execution of the A/D interrupt handling routine ends. 2. 3. 4. 5. 6. 7. After that, if the ADST bit is set to 1, A/D conversion starts again and steps 2 to 7 are repeated. 246 Set * ADIE Set * Set * A/D conversion starts Clear * Clear * ADST ADF Idle State of channel 0 (AN 0) Idle A/D conversion 1 State of channel 1 (AN 1) Idle A/D conversion 2 Idle State of channel 2 (AN 2) Idle Idle 247 State of channel 3 (AN 3) ADDRA Read conversion result A/D conversion result 1 Read conversion result A/D conversion result 2 ADDRB ADDRC ADDRD Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 12-3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) 12.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D data registers corresponding to the channels. When the mode or analog input channel selection must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in the group. The ADST bit can be set at the same time as the mode or channel selection is changed. Typical operations when three channels in group 0 (AN0 to AN2) are selected in scan mode are described next. Figure 12-4 shows a timing diagram for this example. 1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). When A/D conversion of the first channel (AN0) is completed, the result is transferred into ADDRA. Next, conversion of the second channel (AN1) starts automatically. Conversion proceeds in the same way through the third channel (AN2). When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI interrupt is requested at this time. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). 2. 3. 4. 5. 248 Continuous A/D conversion Set *1 Clear*1 ADST Clear* 1 A/D conversion time Idle A/D conversion 1 ADF Idle A/D conversion 4 Idle State of channel 0 (AN 0) Idle A/D conversion 2 Idle State of channel 1 (AN 1) Idle A/D conversion 3 A/D conversion 5 *2 Idle State of channel 2 (AN 2) Idle Transfer A/D conversion result 1 Idle State of channel 3 (AN 3) 249 ADDRA A/D conversion result 4 ADDRB A/D conversion result 2 ADDRC A/D conversion result 3 ADDRD Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored. Figure 12-4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) 12.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 12-5 shows the A/D conversion timing. Table 12-4 indicates the A/D conversion time. As indicated in figure 12-5, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 12-4. In scan mode, the values given in table 12-4 apply to the first conversion. In the second and subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states when CKS = 1 (when oP = o). (1) o Address bus (2) Write signal Input sampling timing ADF tD t SPL t CONV Legend (1): ADCSR write cycle (2): ADCSR address tD : Synchronization delay t SPL : Input sampling time t CONV: A/D conversion time Figure 12-5 A/D Conversion Timing 250 Table 12-4 A/D Conversion Time (Single Mode) CKS = 0 Symbol Synchronization delay Input sampling time* A/D conversion time* tD tSPL tCONV Min 10 -- 259 Typ -- 80 -- Max 17 -- 266 Min 6 -- 131 CKS = 1 Typ -- 40 -- Max 9 -- 134 Note: Values in the table are numbers of states. * Values for when oP = o. When oP = o/2, values are double those given in the table. 12.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR, external trigger input is enabled at the ADTRG pin. A high-to-low transition at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as if the ADST bit had been set to 1 by software. Figure 12-6 shows the timing. o ADTRG Internal trigger signal ADST A/D conversion Figure 12-6 External Trigger Input Timing 12.5 Interrupts The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. 251 12.6 Usage Notes The following points should be noted when using the A/D converter. 1. Analog input voltage range Ensure that the voltage applied to analog input pin ANn (where n = 0 to 7) during A/D conversion is in the range AVSS ANn AVCC. 2. AVCC and AVSS input voltages For the AVCC input voltage, set AVSS = VSS. When the A/D converter is not used, set AVCC = VCC and AVSS = VSS. 252 Section 13 RAM 13.1 Overview The H8/3297 and H8/3296 have 2 kbytes of on-chip static RAM. The H8/3294 has 1 kbyte. The H8/3292 has 512 bytes. The RAM is connected to the CPU by a 16-bit data bus. Both byte and word access to the on-chip RAM are performed in two states, enabling rapid data transfer and instruction execution. The on-chip RAM is assigned to addresses H'F780 to H'FF7F in the address space of the H8/3297 and H8/3296, addresses H'FB80 to H'FF7F in the address space of the H8/3294, and addresses H'FD80 to H'FF7F in the address space of the H8/3292. The RAME bit in the system control register (SYSCR) can enable or disable the on-chip RAM. 13.1.1 Block Diagram Figure 13-1 is a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FB80 H'FB82 H'FB81 H'FB83 On-chip RAM H'FF7E Even address H'FF7F Odd address Figure 13-1 Block Diagram of On-Chip RAM (H8/3297) 253 13.1.2 RAM Enable Bit (RAME) in System Control Register (SYSCR) Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 XRST 1 R 2 NMIEG 0 R/W 1 -- 1 -- 0 RAME 1 R/W The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. See section 3.2, System Control Register, for the other SYSCR bits. Bit 0--RAM Enable (RAME): This bit enables or disables the on-chip RAM. The RAME bit is initialized to 1 on the rising edge of the RES signal. The RAME bit is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled. On-chip RAM is enabled. (Initial value) 13.2 Operation 13.2.1 Expanded Modes (Modes 1 and 2) If the RAME bit is set to 1, accesses to addresses H'F780 to H'FF7F in the H8/3297 and H8/3296, addresses H'FB80 to H'FF7F in the H8/3294, and addresses H'FD80 to H'FF7F in the H8/3292 are directed to the on-chip RAM. If the RAME bit is cleared to 0, accesses to these addresses are directed to the external data bus. 13.2.2 Single-Chip Mode (Mode 3) If the RAME bit is set to 1, accesses to addresses H'F780 to H'FF7F in the H8/3297 and H8/3296, addresses H'FB80 to H'FF7F in the H8/3294, and addresses H'FD80 to H'FF7F in the H8/3292 are directed to the on-chip RAM. If the RAME bit is cleared to 0, the on-chip RAM data cannot be accessed. Attempted write access has no effect. Attempted read access always results in H'FF data being read. Note: RAM initial values are undefined. Therefore initialization must be carried out before use. 254 Section 14 ROM 14.1 Overview The size of the on-chip ROM (mask ROM, or PROM) is 60 kbytes in the H8/3297, 48 kbytes in the H8/3296, 32 kbytes in the H8/3294, and 16kbytes in the H8/3292. The on-chip ROM is connected to the CPU via a 16-bit data bus. Both byte data and word data are accessed in two states, enabling rapid data transfer. The on-chip ROM is enabled or disabled depending on the inputs at the mode pins (MD1 and MD0). See table 14-1. Table 14-1 On-Chip ROM Usage in Each MCU Mode Mode Pins Mode Mode 1 (expanded mode) Mode 2 (expanded mode) Mode 3 (single-chip mode) MD1 0 1 1 MD0 1 0 1 On-chip ROM Disabled (external addresses) Enabled Enabled The PROM versions (H8/3297 ZTAT and H8/3294 ZTAT) can be set to PROM mode and programmed with a general-purpose PROM programmer. In the H8/3297, the accessible ROM addresses are H'0000 to H'EF7F (61,312 bytes) in mode 2, and H'0000 to H'F77F (63,360 bytes) in mode 3. For details, see section 3, MCU Operating Modes and Address Space. 255 14.1.1 Block Diagram Figure 14-1 is a block diagram of the on-chip ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'0000 H'0002 H'0001 H'0003 On-chip ROM H'F77E Even address H'F77F Odd address Figure 14-1 Block Diagram of On-Chip ROM (H8/3297 Single-Chip Mode) 256 14.2 PROM Mode (H8/3297, H8/3294) 14.2.1 PROM Mode Setup In PROM mode the PROM versions of the H8/3297 and H8/3294 suspend, the usual microcomputer functions to allow the on-chip PROM to be programmed. The programming method is the same as for the HN27C101. To select PROM mode, apply the signal inputs listed in table 14-2. Table 14-2 Selection of PROM Mode Pin Mode pin MD1 Mode pin MD0 STBY pin Pins P63 and P64 Input Low Low Low High 14.2.2 Socket Adapter Pin Assignments and Memory Map The H8/3297 and H8/3294 can be programmed with a general-purpose PROM programmer by using a socket adapter to change the pin-out to 32 pins. See table 14-3. The same socket adapter can be used for both the H8/3297 and H8/3294. Figure 14-2 shows the socket adapter pin assignments. Table 14-3 Socket Adapter Package 64-pin QFP 80-pin TQFP 64-pin windowed shrink DIP 64-pin shrink DIP Socket Adapter HS3297ESHS1H HS3297ESNS1H HS3297ESSS1H HS3297ESSS1H The PROM size is 60 kbytes for the H8/3297 and 32 kbytes for the H8/3294. Figures 14-3 and 14-4 show memory maps of the H8/3297 and H8/3294 in PROM mode. H'FF data should be specified for unused address areas in the on-chip PROM. When programming with a PROM programmer, limit the program address range to H'0000 to H'F77F for the H8/3297 and H'0000 to H'7FFF for the H8/3294. Specify H'FF data for addresses H'F780 and above (H8/3297) or H'8000 and above (H8/3294). If these addresses are programmed by mistake, it may become impossible to program or verify the PROM data. The same problem may occur if an attempt is made to program the chip in page programming mode. With a windowed package, it is possible to erase the data and reprogram, but this cannot be done with a plastic package, so particular care is required. 257 H8/3297, H83294 DC-64S DP-64S FP-64A TFP-80C Pin 12 13 57 58 59 60 61 62 63 64 56 55 54 53 52 51 50 49 47 46 45 44 43 42 41 40 1 2 3 34 35 30 14, 39 20 19 15 21 16, 48 4 5 49 50 51 52 53 54 55 56 48 47 46 45 44 43 42 41 39 38 37 36 35 34 33 32 57 58 59 26 27 22 6, 31 12 11 7 13 8, 40 4 5 61 62 63 64 65 67 68 69 60 59 58 57 56 54 53 52 48 47 45 44 43 42 41 40 71 72 74 33 35 27 6, 39 16 14 7 17 12,15,24, 29,31,34, 45,49,50, 51,55,66, 70,73,76 RES NMI P30 P31 P32 P33 P34 P35 P36 P37 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P40 P41 P42 P63 P64 AVCC VCC MD0 MD1 STBY AVSS EP ROM Socket Pin VPP EA9 EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 OE EA10 EA11 EA12 EA13 EA14 CE EA16 EA15 PGM VCC HN27C 101 (32 pins) 1 26 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 22 2 3 31 32 VSS 16 8, 9, 10, VCC VPP : Program voltage (12.5V) EO7 to EO0 : Data input/output EA16 to EA0 : Address input OE : Output enable CE : Chip enable PGM : Program enable Note: All pins not listed in this figure should be left open. Figure 14-2 Socket Adapter Pin Assignments 258 Address in MCU mode H'0000 Address in PROM mode H'0000 On-chip PROM H'F77F Undetermined volume output* H'F77F Note: * If this address area is read in PROM mode, the output data is not guaranteed. H'1FFFF Figure 14-3 H8/3297 Memory Map in PROM Mode Address in MCU mode H'0000 Address in PROM mode H'0000 On-chip PROM H'7FFF H'7FFF Undetermined volume output* Note: * If this address area is read in PROM mode, the output data is not guaranteed. H'1FFFF Figure 14-4 H8/3294 Memory Map in PROM Mode 259 14.3 PROM Programming The write, verify, and other sub-modes of the PROM mode are selected as shown in table 14-4. Table 14-4 Selection of Sub-Modes in PROM Mode Sub-Mode Write Verify Programming inhibited CE Low Low Low Low High High OE High Low Low High Low High PGM Low High Low High Low High VPP VPP VPP VPP VCC VCC VCC VCC EO7 to EO0 Data input Data output High impedance EA16 to EA0 Address input Address input Address input The H8/3297 and H8/3294 PROM have the same standard read/write specifications as the HN27C101 EPROM. Page programming is not supported, however, so do not select page programming mode. PROM programmers that provide only page programming cannot be used. When selecting a PROM programmer, check that it supports a byte-at-a-time high-speed programming mode. Be sure to set the address range to H'0000 to H'F77F for the H8/3297, and to H'0000 to H'7FFF for the H8/3294. 14.3.1 Programming and Verifying An efficient, high-speed programming procedure can be used to program and verify PROM data. This procedure programs data quickly without subjecting the chip to voltage stress and without sacrificing data reliability. It leaves the data H'FF in unused addresses. 260 Figure 14-5 shows the basic high-speed programming flowchart. Tables 14-5 and 14-6 list the electrical characteristics of the chip in PROM mode. Figure 14-6 shows a program/verify timing chart. Start Set program/verify mode VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V Address = 0 n=0 n + 1 n Program tPW = 0.2 ms 5% No Yes n < 25? No Verify OK? Yes Program tOPW = 0.2n ms No Address + 1 address Last address? Yes Set read mode VCC = 5.0 V 0.25 V, VPP = VCC Error No go Read all addresses Go End Figure 14-5 High-Speed Programming Flowchart 261 Table 14-5 DC Characteristics (when VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current VCC current VPP current EO7 - EO0, A16 - A0, OE, CE, PGM EO7 - EO0, A16 - A0, OE, CE, PGM EO7 - EO0 EO7 - EO0 EO7 - EO0, EA16 - EA0, OE, CE, PGM Symbol VIH Min 2.4 Typ -- Max VCC + 0.3 Unit V Test Conditions VIL -0.3 -- 0.8 V VOH VOL |ILI| 2.4 -- -- -- -- -- -- 0.45 2 V V A IOH = -200 A IOL = 1.6 mA Vin = 5.25 V/0.5 V ICC IPP -- -- -- -- 40 40 mA mA Table 14-6 AC Characteristics (when VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C) Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time VPP setup time Program pulse width Symbol tAS tOES tDS tAH tDH tDF tVPS tPW Min 2 2 2 0 2 -- 2 0.19 Typ -- -- -- -- -- -- -- 0.20 Max -- -- -- -- -- 130 -- 0.21 Unit s s s s s ns s ms Test Conditions See figure 14-6* Note: * Input pulse level: 0.8 V to 2.2 V Input rise/fall time 20 ns Timing reference levels: input--1.0 V, 2.0 V; output--0.8 V, 2.0 V 262 Table 14-6 AC Characteristics (cont) (when VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C) Item OE pulse width for overwrite-programming VCC setup time CE setup time Data output delay time Symbol tOPW tVCS tCES tOE Min 0.19 2 2 0 Typ -- -- -- -- Max 5.25 -- -- 150 Unit ms s s ns Test Conditions See figure 14-6* Note: * Input pulse level: 0.8 V to 2.2 V Input rise/fall time 20 ns Timing reference levels: input--1.0 V, 2.0 V; output--0.8 V, 2.0 V Write Address tAS Data tDS VPP VPP VCC VCC + 1 VCC tVCS tVPS Input data tDH Verify tAH Output data tDF VCC CE tCES PGM tPW OE tOPW tOES tOE Figure 14-6 PROM Program/Verify Timing 263 14.3.2 Notes on Programming (1) Program with the specified voltages and timing. The programming voltage (VPP) is 12.5 V. Caution: Applied voltages in excess of the specified values can permanently destroy the chip. Be particularly careful about the PROM programmer's overshoot characteristics. If the PROM programmer is set to HN27C101 specifications, VPP will be 12.5 V. (2) Before writing data, check that the socket adapter and chip are correctly mounted in the PROM writer. Overcurrent damage to the chip can result if the index marks on the PROM programmer, socket adapter, and chip are not correctly aligned. (3) Don't touch the socket adapter or chip while writing. Touching either of these can cause contact faults and write errors. (4) Page programming is not supported. Do not select page programming mode. (5) The H8/3297 PROM size is 60 kbytes. The H8/3294 PROM size is 32 kbytes. Set the address range to H'0000 to H'F77F for the H8/3297, and to H'0000 to H'7FFF for the H8/3294. When programming, specify H'FF data for unused address areas (H'F780 to H'1FFFF in the H8/3297, H'8000 to H'1FFFF in the H8/3294). 14.3.3 Reliability of Programmed Data An effective way to assure the data holding characteristics of the programmed chips is to bake them at 150C, then screen them for data errors. This procedure quickly eliminates chips with PROM memory cells prone to early failure. Figure 14-7 shows the recommended screening procedure. 264 Write and verify program Bake chip for 24 to 48 hours at 125C to 150C with power off Read and check program VCC = 5 V Install Figure 14-7 Recommended Screening Procedure If a series of write errors occurs while the same PROM programmer is in use, stop programming and check the PROM programmer and socket adapter for defects, using a microcomputer chip with a windowed package and on-chip EPROM. Please inform Hitachi of any abnormal conditions noted during programming or in screening of program data after high-temperature baking. 14.3.4 Erasing of Data The windowed package enables data to be erased by illuminating the window with ultraviolet light. Table 14-7 lists the erasing conditions. Table 14-7 Erasing Conditions Item Ultraviolet wavelength Minimum illumination Value 253.7 nm 15 W*s/cm2 The conditions in table 14-7 can be satisfied by placing a 12000 W/cm2 ultraviolet lamp 2 or 3 centimeters directly above the chip and leaving it on for about 20 minutes. 265 14.4 Handling of Windowed Packages (1) Grass Erasing Window: Rubbing the glass erasing window of a windowed package with a plastic material or touching it with an electrically charged object can create a static charge on the window surface which may cause the chip to malfunction. If the erasing window becomes charged, the charge can be neutralized by a short exposure to ultraviolet light. This returns the chip to its normal condition, but it also reduces the charge stored in the floating gates of the PROM, so it is recommended that the chip be reprogrammed afterward. Accumulation of static charge on the window surface can be prevented by the following precautions: 1. 2. 3. 4. When handling the package, ground yourself. Don't wear gloves. Avoid other possible sources of static charge. Avoid friction between the glass window and plastic or other materials that tend to accumulate static charge. Be careful when using cooling sprays, since they may have a slight icon content. Cover the window with an ultraviolet-shield label, preferably a label including a conductive material. Besides protecting the PROM contents from ultraviolet light, the label protects the chip by distributing static charge uniformly. (2) Handling after Programming: Fluorescent light and sunlight contain small amounts of ultraviolet, so prolonged exposure to these types of light can cause programmed data to invert. In addition, exposure to any type of intense light can induce photoelectric effects that may lead to chip malfunction. It is recommended that after programming the chip, you cover the erasing window with a light-proof label (such as an ultraviolet-shield label). 266 Section 15 Power-Down State 15.1 Overview The H8/3297 Series has a power-down state that greatly reduces power consumption by stopping some or all of the chip functions. The power-down state includes three modes: (1) Sleep mode (2) Software standby mode (3) Hardware standby mode Table 15-1 lists the conditions for entering and leaving the power-down modes. It also indicates the status of the CPU, on-chip supporting modules, etc. in each power-down mode. Table 15-1 Power-Down State Mode Sleep mode Software standby mode Entering Procedure Execute SLEEP instruction Set SSBY bit in SYSCR to 1, then execute SLEEP instruction Set STBY pin to low level Clock Run CPU Halt Reg's. Held CPU Mod. Run Sup. RAM Held I/O Ports Held Exiting Methods * Interrupt * RES * STBY * * * * NMI IRQ0 to IRQ2 RES STBY Halt Halt Held Halt and initialized Held Held Hardware standby mode Halt Halt Not held Halt Held and initialized High impedance state * STBY and RES Notes: 1. SYSCR: System control register 2. SSBY: Software standby bit 267 15.1.1 System Control Register (SYSCR) Four of the eight bits in the system control register (SYSCR) control the power-down state. These are bit 7 (SSBY) and bits 6 to 4 (STS2 to STS0). See table 15-2. Table 15-2 System Control Register Name System control register Bit Initial value Read/Write 7 SSBY 0 R/W Abbreviation SYSCR 6 STS2 0 R/W 5 STS1 0 R/W R/W R/W 4 STS0 0 R/W Initial Value H'0B 3 XRST 1 R 2 NMIEG 0 R/W Address H'FFC4 1 -- 1 -- 0 RAME 1 R/W Bit 7--Software Standby (SSBY): This bit enables or disables the transition to software standby mode. On recovery from the software standby mode by an external interrupt, SSBY remains set to 1. To clear this bit, software must write a 0. Bit 7 SSBY 0 1 Description The SLEEP instruction causes a transition to sleep mode. The SLEEP instruction causes a transition to software standby mode. (Initial value) 268 Bits 6 to 4--Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling time when the chip recovers from software standby mode by an external interrupt. During the selected time, the clock oscillator runs but the CPU and on-chip supporting modules remain in standby. Set bits STS2 to STS0 according to the clock frequency to obtain a settling time of at least 8 ms. See table 15-3. Bit 6 STS2 0 0 0 0 1 1 Bit 5 STS1 0 0 1 1 0 1 Bit 4 STS0 0 1 0 1 -- -- Description Settling time = 8,192 states Settling time = 16,384 states Settling time = 32,768 states Settling time = 65,536 states Settling time = 131,072 states Disabled (Initial value) 15.2 Sleep Mode 15.2.1 Transition to Sleep Mode When the SSBY bit in the system control register is cleared to 0, execution of the SLEEP instruction causes a transition from the program execution state to sleep mode. After executing the SLEEP instruction, the CPU halts, but the contents of its internal registers remain unchanged. The on-chip supporting modules continue to operate normally. 15.2.2 Exit from Sleep Mode The chip exits sleep mode when it receives an internal or external interrupt request, or a low input at the RES or STBY pin. (1) Exit by Interrupt: An interrupt releases sleep mode and starts the CPU's interrupt-handling sequence. If an interrupt from an on-chip supporting module is disabled by the corresponding enable/disable bit in the module's control register, the interrupt cannot be requested, so it cannot wake the chip up. Similarly, the CPU cannot be awoken by an interrupt other than NMI if the I (interrupt mask) bit is set when the SLEEP instruction is executed. (2) Exit by RES pin: When the RES pin goes low, the chip exits from sleep mode to the reset state. (3) Exit by STBY pin: When the STBY pin goes low, the chip exits from sleep mode to hardware standby mode. 269 15.3 Software Standby Mode 15.3.1 Transition to Software Standby Mode To enter software standby mode, set the standby bit (SSBY) in the system control register (SYSCR) to 1, then execute the SLEEP instruction. In software standby mode, the system clock stops and chip functions halt, including both CPU functions and the functions of the on-chip supporting modules. Power consumption is reduced to an extremely low level. The on-chip supporting modules and their registers are reset to their initial states, but as long as a minimum necessary voltage supply is maintained, the contents of the CPU registers and on-chip RAM remain unchanged. 15.3.2 Exit from Software Standby Mode The chip can be brought out of software standby mode by by RES input, STBY input, or external interrupt input at the NMI pin, IRQ0 to IRQ2 pins. (1) Exit by Interrupt: When an NMI, IRQ0, IRQ1,or IRQ2 interrupt request signal is input, the clock oscillator begins operating. After the waiting time set in bits STS2 to STS0 of SYSCR, a stable clock is supplied to the entire chip, software standby mode is released, and interrupt exception-handling begins. (2) Exit by RES Pin: When the RES input goes low, the clock oscillator begins operating. When RES is brought to the high level (after allowing time for the clock oscillator to settle), the CPU starts reset exception handling. Be sure to hold RES low long enough for clock oscillation to stabilize. (3) Exit by STBY Pin: When the STBY input goes low, the chip exits from software standby mode to hardware standby mode. 270 15.3.3 Clock Settling Time for Exit from Software Standby Mode Set bits STS2 to STS0 in SYSCR as follows: * Crystal oscillator Set STS2 to STS0 for a settling time of at least 10 ms. Table 15-3 lists the settling times selected by these bits at several clock frequencies. * External clock The STS bits can be set to any value. Normally, use of the minimum time is recommended (STS2 = STS1 = STS0 = 0). Table 15-3 Times Set by Standby Timer Select Bits (Unit: ms) Settling Time STS2 STS1 STS0 (States) 16 0 0 0 0 1 0 0 1 1 0 0 1 0 1 -- 8,192 16,384 32,768 65,536 0.51 1.0 2.0 4.1 System Clock Frequency (MHz) 12 0.65 1.3 2.7 5.5 10.9 10 0.8 1.6 3.3 6.6 13.1 8 1.0 2.0 4.1 8.2 16.4 6 1.3 2.7 5.5 10.9 21.8 4 2.0 4.1 8.2 16.4 32.8 2 4.1 8.2 16.4 32.8 65.5 1 8.2 16.4 32.8 65.5 0.5 16.4 32.8 65.5 131.1 131,072 8.2 131.1 262.1 Notes: 1. All times are in milliseconds. 2. Recommended values are printed in boldface. 271 15.3.4 Sample Application of Software Standby Mode In this example the chip enters the software standby mode when NMI goes low and exits when NMI goes high, as shown in figure 15-1. The NMI edge bit (NMIEG) in the system control register is originally cleared to 0, selecting the falling edge. When NMI goes low, the NMI interrupt handling routine sets NMIEG to 1, sets SSBY to 1 (selecting the rising edge), then executes the SLEEP instruction. The chip enters software standby mode. It recovers from software standby mode on the next rising edge of NMI. Clock oscillator o NMI NMIEG SSBY NMI interrupt handler NMIEG = 1 SSBY = 1 Software standby mode (powerdown state) Setting time NMI interrupt handler SLEEP Figure 15-1 NMI Timing in Software Standby Mode 15.3.5 Usage Note The I/O ports retain their current states in software standby mode. If a port is in the high output state, the current dissipation caused by the output current is not reduced. 272 15.4 Hardware Standby Mode 15.4.1 Transition to Hardware Standby Mode Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin goes low. Hardware standby mode reduces power consumption drastically by halting the CPU, stopping all the functions of the on-chip supporting modules, and placing I/O ports in the high-impedance state. The registers of the on-chip supporting modules are reset to their initial values. Only the on-chip RAM is held unchanged, provided the minimum necessary voltage supply is maintained. Notes: 1. The RAME bit in the system control register should be cleared to 0 before the STBY pin goes low. 2. Do not change the inputs at the mode pins (MD1, MD0) during hardware standby mode. Be particularly careful not to let both mode pins go low in hardware standby mode, since that places the chip in PROM mode and increases current dissipation. 15.4.2 Recovery from Hardware Standby Mode Recovery from the hardware standby mode requires inputs at both the STBY and RES pins. When the STBY pin goes high, the clock oscillator begins running. The RES pin should be low at this time and should be held low long enough for the clock to stabilize. When the RES pin changes from low to high, the reset sequence is executed and the chip returns to the program execution state. 273 15.4.3 Timing Relationships Figure 15-2 shows the timing relationships in hardware standby mode. In the sequence shown, first RES goes low, then STBY goes low, at which point the chip enters hardware standby mode. To recover, first STBY goes high, then after the clock settling time, RES goes high. Clock pulse generator RES STBY Clock setting time Reset Figure 15-2 Hardware Standby Mode Timing 274 Section 16 Electrical Specifications 16.1 Absolute Maximum Ratings Table 16-1 lists the absolute maximum ratings. Table 16-1 Absolute Maximum Ratings Item Supply voltage Programming voltage Input voltage Ports 1 to 6 Port 7 Analog supply voltage Analog input voltage Operating temperature Symbol VCC VPP Vin Vin AVCC VAN Topr Tstg Rating -0.3 to +7.0 -0.3 to +13.5 -0.3 to VCC + 0.3 -0.3 to AVCC + 0.3 -0.3 to +7.0 -0.3 to AVCC + 0.3 Regular specifications: -20 to +75 Wide-range specifications: -40 to +85 Storage temperature -55 to +125 Unit V V V V V V C C C Note: Exceeding the absolute maximum ratings shown in table 16-1 can permanently destroy the chip. 16.2 Electrical Characteristics 16.2.1 DC Characteristics The DC characteristics of the 5 V, 4 V, and 3 V versions are shown in tables 16-2, 16-3, and 16-4 respectively. The allowable output current values for the 5 V and 4 V versions are shown in table 16-5, and those for the 3 V version in table 16-6. 275 Table 16-2 DC Characteristics (5-V Version) Conditions: VCC = 5.0 V 10%, AVCC = 5.0 V 10%*1, VSS = AVSS = 0 V, Ta = -20 to 75C (regular specifications), Ta = -40 to 85C (wide-range specifications) Item Schmitt trigger input voltage (1) Input high voltage (2) P67 to P60*4, IRQ2 to IRQ0*5 Symbol VT- VT + + - Min 1.0 -- 0.4 Typ -- -- -- Max -- VCC x 0.7 -- VCC + 0.3 Test Unit Conditions V VT - VT RES, STBY, NMI MD1, MD0 EXTAL P77 to P70 Input high voltage Input low voltage (3) Input low voltage Output high voltage Output low voltage Input leakage current Input pins other than (1) and (2) RES, STBY MD1, MD0 Input pins other than (1) and (3) above All output pins VIH VIH VCC - 0.7 -- V 2.0 2.0 -- -- AVCC + 0.3 VCC + 0.3 VIL VIL -0.3 -0.3 -- -- 0.5 0.8 V VOH VOL |Iin| VCC - 0.5 -- 3.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.4 1.0 10.0 1.0 1.0 1.0 V IOH = -200 A IOH = -1.0 mA IOL = 1.6 mA IOL = 10.0 mA Vin = 0.5 V to VCC - 0.5 V Vin = 0.5 V to AVCC - 0.5 V All output pins Ports 1 and 2 RES, STBY NMI, MD1, MD0 P77 to P70 V A Leakage current in 3-state (off state) Input pull-up MOS current Ports 1 to 6 |ITSI| -- A Vin = 0.5 V to VCC - 0.5 V Ports 1, 2, 3 -Ip 30 -- 250 A Vin = 0 V Refer to notes at the end of the table. 276 Table 16-2 DC Characteristics (5-V Version) (cont) Conditions: VCC = 5.0 V 10%, AVCC = 5.0 V 10%*1, VSS = AVSS = 0 V, Ta = -20 to 75C (regular specifications), Ta = -40 to 85C (wide-range specifications) Item Input capacitance RES, STBY NMI, MD1 All input pins except RES, STBY, NMI and MD1 Current dissipation*2 Normal operation Sleep mode ICC Symbol Cin Min -- -- -- Typ -- -- -- Max 60 30 15 Test Unit Conditions pF Vin = 0 V f = 1 MHz Ta = 25C -- -- -- -- 27 36 18 24 45 60 30 40 mA f = 12 MHz f = 16 MHz f = 12 MHz f = 16 MHz Ta 50C 50C < Ta Standby modes*3 -- -- 0.01 5.0 -- 2.0 20.0 5.0 A A mA A V Analog supply current During A/D conversion AICC -- -- Waiting AVCC 0.01 5.0 -- -- 5.5 5.5 AVCC = 2.0 V to 5.5 V During operation During wait state or when not in use Analog supply voltage*1 4.5 2.0 RAM standby voltage VRAM 2.0 -- -- V Notes: 1. Even when the A/D converter is not used, connect AVCC to power supply VCC and keep the applied voltage between 2.0 V and 5.5 V. 2. Current dissipation values assume that VIH min = VCC - 0.5 V, VIL max = 0.5 V, all output pins are in the no-load state, and all input pull-up transistors are off. 3. For these values it is assumed that VRAM VCC < 4.5 V and VIH min = VCC x 0.9, VIL max = 0.3 V. 4. P67 to P60 include supporting module inputs multiplexed with them. 5. IRQ2 includes ADTRG multiplexed with it. 277 Table 16-3 DC Characteristics (4-V Version) Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V*1, VSS = AVSS = 0 V, Ta = -20 to 75C (regular specifications), Ta = -40 to 85C (wide-range specifications) Item Schmitt trigger input voltage (1) P67 to P60*4, IRQ2 to IRQ0*5 Symbol VT- VT VT VT Input high voltage (2) RES, STBY, NMI MD1, MD0 EXTAL P77 to P70 Input high voltage Input low voltage (3) Input low voltage Input pins other than (1) and (2) RES, STBY MD1, MD0 Input pins other than (1) and (3) above VIL + + - + + - - Min 1.0 -- 0.4 0.8 -- 0.3 Typ -- -- -- -- -- -- Max -- VCC x 0.7 -- -- VCC x 0.7 -- VCC + 0.3 Test Unit Conditions V VCC = 4.5 V to 5.5 V VT - VT VCC = 4.0 V to 4.5 V VT - VT VIH VCC - 0.7 -- V 2.0 2.0 -- -- AVCC + 0.3 VCC + 0.3 -0.3 -0.3 -0.3 -- -- -- 0.5 0.8 0.6 -- -- V VCC = 4.5 V to 5.5 V VCC = 4.0 V to 4.5 V V IOH = -200 A IOH = -1.0 mA VCC = 4.5 V to 5.5 V IOH = -1.0 mA VCC = 4.0 V to 4.5 V V IOL = 1.6 mA IOL = 10.0 mA V Vin = 0.5 V to VCC - 0.5 V Vin = 0.5 V to AVCC - 0.5 V Output high voltage All output pins VOH VCC - 0.5 -- 3.5 -- 2.8 -- -- Output low voltage Input leakage current All output pins P17 to P10, P27 to P20 RES, STBY NMI, MD1, MD0 P77 to P70 VOL |Iin| -- -- -- -- -- -- -- -- -- -- 0.4 1.0 10.0 1.0 1.0 A Refer to notes at the end of the table. 278 Table 16-3 DC Characteristics (4-V Version) (cont) Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V*1, VSS = AVSS = 0 V, Ta = -20 to 75C (regular specifications), Ta = -40 to 85C (wide-range specifications) Item Leakage current in 3-state (off state) Input pull-up MOS current Ports 1 to 6 Symbol |ITSI| Min -- Typ -- Max 1.0 Test Unit Conditions A Vin = 0.5 V to VCC - 0.5 V Ports 1, 2, 3 -Ip 30 -- 250 A Vin = 0 V VCC = 4.5 V to 5.5 V Vin = 0 V VCC = 4.0 V to 4.5 V 20 -- 200 Input capacitance RES, STBY NMI, MD1 All input pins except RES, STBY, NMI and MD1 Cin -- -- -- -- -- -- 60 30 15 pF Vin = 0 V f = 1 MHz Ta = 25C Current dissipation*2 Normal operation ICC -- -- 27 36 45 60 mA f = 12 MHz f = 16 MHz VCC = 4.5 V to 5.5 V f = 12 MHz f = 16 MHz VCC = 4.5 V to 5.5 V Sleep mode -- -- 18 24 30 40 Standby modes*3 -- -- 0.01 5.0 -- 2.0 20.0 5.0 A Ta 50C 50C < Ta Analog supply current During A/D conversion AICC -- -- mA A V AVCC = 2.0 V to 5.5 V During operation During wait state or when not in use V Waiting AVCC 0.01 5.0 -- -- 5.5 5.5 Analog supply voltage*1 4.0 2.0 RAM standby voltage VRAM 2.0 -- -- Refer to notes at the end of the table. 279 Notes: 1. Even when the A/D converter is not used, connect AVCC to power supply VCC and keep the applied voltage between 2.0 V and 5.5 V. 2. Current dissipation values assume that VIH min = VCC - 0.5 V, VIL max = 0.5 V, all output pins are in the no-load state, and all input pull-up transistors are off. 3. For these values it is assumed that VRAM VCC < 4.0 V and VIH min = VCC x 0.9, VIL max = 0.3 V. 4. P67 to P60 include supporting module inputs multiplexed with them. 5. IRQ2 includes ADTRG multiplexed with it. 280 Table 16-4 DC Characteristics (3-V Version) Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V*1, VSS = AVSS = 0 V, Ta = -20 to 75C Item Schmitt trigger input voltage (1) Input high voltage (2) P67 to P60*4, IRQ2 to IRQ0*5 Symbol VT- VT+ Min Typ Max -- VCC x 0.7 -- VCC + 0.3 V Test Unit Conditions V VCC x 0.15 -- -- -- -- VT+ - VT- 0.2 RES, STBY MD1, MD0 EXTAL, NMI P77 to P70 VIH VCC x 0.9 -- VCC x 0.7 -- VCC x 0.7 -- AVCC + 0.3 VCC + 0.3 Input high voltage Input low voltage (3) Input low voltage Output high voltage Output low voltage Input leakage current Input pins other than (1) and (2) above RES, STBY MD1, MD0 Input pins other than (1) and (3) above All output pins VOH VOL |Iin| VIL -0.3 -0.3 -- -- VCC x 0.1 VCC x 0.15 V VCC - 0.5 -- VCC - 1.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.4 0.4 10.0 1.0 1.0 1.0 V IOH = -200 A IOH = -1.0 mA IOL = 0.8 mA IOL = 1.6 mA Vin = 0.5 V to VCC - 0.5 V Vin = 0.5 V to AVCC - 0.5 V All output pins Ports 1 and 2 RES, STBY NMI, MD1, MD0 P77 to P70 V A Leakage current in 3-state (off state) Input pull-up MOS current Ports 1 to 6 |ITSI| -- A Vin = 0.5 V to VCC - 0.5 V Ports 1, 2, 3 -Ip 3 -- 120 A Vin = 0 V, VCC = 2.7 V to 4.0 V Refer to notes at the end of the table. 281 Table 16-4 DC Characteristics (3-V Version) (cont) Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V*1, VSS = AVSS = 0 V, Ta = -20 to 75C Item Input capacitance RES, STBY NMI, MD1 All input pins except RES, STBY , NMI and MD1 Current dissipation*2 Normal operation ICC Symbol Cin Min -- -- -- Typ -- -- -- Max 60 30 15 Test Unit Conditions pF Vin = 0 V f = 1 MHz Ta = 25C -- -- -- 7 12 25 5 9 18 -- 22 -- -- 16 -- mA f = 6 MHz VCC = 2.7 V to 3.6 V f = 10 MHz, VCC = 2.7 V to 3.6 V f = 10 MHz, VCC = 4.0 V to 5.5 V f = 6 MHz VCC = 2.7 V to 3.6 V f = 10 MHz VCC = 2.7 V to 3.6 V f = 10 MHz VCC = 4.0 V to 5.5 V Sleep mode -- -- -- Standby modes*3 -- -- 0.01 5.0 -- 2.0 20.0 5.0 A A mA A V Ta 50C 50C < Ta Analog supply current During A/D conversion AICC -- -- Waiting AVCC 0.01 5.0 -- -- 5.5 5.5 AVCC = 2.0 V to 5.5 V During operation During wait state or when not in use Analog supply voltage*1 2.7 2.0 RAM backup voltage (in standby modes) VRAM 2.0 -- -- V Notes: 1. Even when the A/D converter is not used, connect AVCC to power supply VCC and keep the applied voltage between 2.0 V and 5.5 V. 2. Current dissipation values assume that VIH min = VCC - 0.5 V, VIL max = 0.5 V, all output pins are in the no-load state, and all input pull-up transistors are off. 3. For these values it is assumed that VRAM VCC < 2.7 V and VIH min = VCC x 0.9, VIL max = 0.3 V. 4. P67 to P60 include supporting module inputs multiplexed with them. 5. IRQ2 includes ADTRG multiplexed with it. 282 Table 16-5 Allowable Output Current Values (5-V Version 4-V Version) Conditions: VCC = 4.0 V to 5.5V, AVCC = 4.0 V to 5.5V, VSS = AVSS = 0 V, Ta = -20 to 75C (regular specifications), Ta = -40 to 85C (wide-range specifications) Item Allowable output low Ports 1 and 2 Other output pins Allowable output low current (total) Allowable output high current (per pin) Allowable output high current (total) Ports 1 and 2, total Total of all output All output pins Total of all output -IOH -IOH IOL Symbol IOL-- Min -- -- -- -- -- -- Typ 10 -- -- -- -- -- Max mA 2 80 120 2 40 mA mA mA Unit Table 16-6 Allowable Output Current Values (3-V Version) Conditions: VCC = 2.7 to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = -20 to 75C Item Allowable output low Ports 1 and 2 Other output pins Allowable output low current (total) Allowable output high current (per pin) Allowable output high current (total) Ports 1 and 2, total Total of all output All output pins Total of all output -IOH -IOH IOL Symbol IOL Min -- -- -- -- -- -- Typ -- -- -- -- -- -- Max 2 1 40 60 2 30 mA mA mA Unit mA Note: To avoid degrading the reliability of the chip, be careful not to exceed the output current values in tables 16-5 and 16-6. In particular, when driving a darlington transistor pair or LED directly, be sure to insert a current-limiting resistor in the output path. See figures 16-1 and 16-2. 283 H8/3297 2 k Port Darlington pair Figure 16-1 Example of Circuit for Driving a Darlington Pair (5-V Version) H8/3297 VCC 600 Ports 1 or 2 LED Figure 16-2 Example of Circuit for Driving an LED (5-V Version) 284 16.2.2 AC Characteristics The AC characteristics are listed in three tables. Bus timing parameters are given in table 16-7, control signal timing parameters in table 16-8, and timing parameters of the on-chip supporting modules in table 16-9. Table 16-7 Bus Timing Condition A: VCC = 5.0 V 10%, VSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to 75C (regular specifications), Ta = -40 to 85C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5V, VSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to 75C (regular specifications), Ta = -40 to 85C (wide-range specifications) Condition C: VCC = 2.7 V to 5.5 V, VSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to 75C Condition C 10 MHz Item Clock cycle time Clock pulse width low Clock pulse width high Clock rise time Clock fall time Address delay time Address hold time Address strobe delay time Write strobe delay time Strobe delay time Write strobe pulse width* Address setup time 1* Address setup time 2* Read data setup time Read data hold time* Read data access time* Write data delay time Write data setup time Write data hold time Wait setup time Wait hold time Symbol tcyc tCL tCH tCr tCf tAD tAH tASD tWSD tSD tWSW tAS1 tAS2 tRDS tRDH tACC tWDD tWDS tWDH tWTS tWTH Min 100 30 30 - - - 20 - - - 110 15 65 35 0 - - 5 20 40 10 Max 500 - - 20 20 50 - 50 50 50 - - - - - 170 75 - - - - Condition B 12 MHz Min 83.3 30 30 - - - 15 - - - 90 10 50 20 0 - - 5 20 35 10 Max 500 - - 10 10 35 - 35 35 35 - - - - - 160 60 - - - - Condition A 16 MHz Min 62.5 20 20 - - - 10 - - - 60 10 40 20 0 - - 5 20 30 10 Max 500 - - 10 10 30 - 30 30 30 - - - - - 110 60 - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Fig. 16-4 Fig. 16-4 Fig. 16-4 Fig. 16-4 Fig. 16-4 Fig. 16-4 Fig. 16-4 Fig. 16-4 Fig. 16-4 Fig. 16-4 Fig. 16-4 Fig. 16-4 Fig. 16-4 Fig. 16-4 Fig. 16-4 Fig. 16-4 Fig. 16-4 Fig. 16-4 Fig. 16-4 Fig. 16-5 Fig. 16-5 Note: * Values at maximum operating frequency 285 Table 16-8 Control Signal Timing Condition A: VCC = 5.0 V 10%, VSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to 75C (regular specifications), Ta = -40 to 85C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to 75C (regular specifications), Ta = -40 to 85C (wide-range specifications) Condition C: VCC = 2.7 V to 5.5 V, VSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to 75C Condition C 10 MHz Item RES setup time RES pulse width NMI setup time (NMI, IRQ0 to IRQ2) NMI hold time (NMI, IRQ0 to IRQ2) Interrupt pulse width for recovery from software standby mode (NMI, IRQ0 to IRQ2) Crystal oscillator settling time (reset) Crystal oscillator settling time (software standby) Symbol tRESS tRESW tNMIS tNMIH tNMIW Min 300 10 300 10 300 Max - - - - - Condition B 12 MHz Min 200 10 150 10 200 Max - - - - - Condition A 16 MHz Min 200 10 150 10 200 Max - - - - - Unit ns tcyc ns ns ns Test Conditions Fig. 16-6 Fig. 16-6 Fig. 16-7 Fig. 16-7 Fig. 16-7 tOSC1 tOSC2 20 8 - - 20 8 - - 20 8 - - ms ms Fig. 16-8 Fig. 16-9 * Measurement Conditions for AC Characteristics 5V RL LSI output pin RH C C = 90 pF: Ports 1 to 4, 6 30 pF: Port 5 RL = 2.4 k RH = 12 k Input/output timing measurement levels Low: 0.8 V High: 2.0 V Figure 16-3 Measurement Conditions for A/C Characteristics 286 Table 16-9 Timing Conditions of On-Chip Supporting Modules Condition A: VCC = 5.0 V 10%, VSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to 75C (regular specifications), Ta = -40 to 85C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to 75C (regular specifications), Ta = -40 to 85C (wide-range specifications) Condition C: VCC = 2.7 V to 5.5 V, VSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to 75C Condition C 10 MHz Min Max - 80 80 1.5 - 80 80 1.5 2.5 4 6 - 150 150 0.4 - 80 80 150 - - - 150 - - - - - - 200 - - 0.6 150 - - Condition B 12 MHz Min Max - 50 50 1.5 - 50 50 1.5 2.5 4 6 - 100 100 0.4 - 50 50 100 - - - 100 - - - - - - 100 - - 0.6 100 - - Condition A 16 MHz Min Max - 50 50 1.5 - 50 50 1.5 2.5 4 6 - 100 100 0.4 - 50 50 100 - - - 100 - - - - - - 100 - - 0.6 100 - - Test Conditions Fig. 16-10 Fig. 16-10 Fig. 16-11 Fig. 16-11 Fig. 16-12 Fig. 16-14 Fig. 16-13 Fig. 16-13 Fig. 16-13 Fig. 16-15 Fig. 16-15 Fig. 16-15 Fig. 16-15 Fig. 16-15 Fig. 16-16 Fig. 16-17 Fig. 16-17 Fig. 16-17 Item FRT Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width TMR Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width (single edge) Timer clock pulse width (both edges) SCI Symbol tFTOD tFTIS tFTCS tFTCWH tFTCWL tTMOD tTMRS tTMCS tTMCWH tTMCWL Unit ns ns ns tcyc ns ns ns tcyc tcyc tcyc tcyc ns ns ns tScyc ns ns ns Input clock (Async) tScyc cycle (Sync) tScyc Transmit data delay time (Sync) Receive data setup time (Sync) Receive data hold time (Sync) Input clock pulse width tTXD tRXS tRXH tSCKW tPWD tPRS tPRH Ports Output data delay time Input data setup time Input data hold time 287 Table 16-10 External Clock Output Delay Timing Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = -40 to +85C Condition Item External clock output delay time Symbol tDEXT Min 500 Max -- Unit s Test Conditions Fig. 16-18 Note: * tDEXT includes RES pulse width tRESW (10 tcyc). 288 16.2.3 A/D Converter Characteristics Table 16-11 lists the characteristics of the on-chip A/D converter. Table 16-11 A/D Converter Characteristics Condition A: VCC = 5.0 V 10%, VCCB = 5.0 V 10%, AVCC = 5.0 V 10%, AVref = 4.5 V to AVCC, VSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B: VCC = 4.0 V to 5.5 V, VCCB = 4.0 to 5.5 V, AVCC = 4.0 to 5.5 V, AVref = 4.0 to AVCC,, VSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition C: VCC = 2.7 to 5.5 V, VCCB = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, AVref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2.0 MHz to maximum operating frequency, Ta = -20 to +75C Condition C 10 MHz Item Resolution Conversion time (single mode)* Analog input capacitance Allowable signal source impedance Nonlinearity error Offset error Full-scale error Quantizing error Absolute accuracy Min Typ Max 10 -- -- -- -- -- -- -- -- 10 -- -- -- -- -- -- -- -- 10 13.4 20 5 6.0 4.0 4.0 0.5 8.0 Condition B 12 MHz Min Typ 10 -- -- -- -- -- -- -- -- 10 -- -- -- -- -- -- -- -- Max 10 11.2 20 10 3.0 3.5 3.5 0.5 4.0 Min 10 -- -- -- -- -- -- -- -- Condition A 16 MHz Typ 10 -- -- -- -- -- -- -- -- Max 10 8.4 20 10 3.0 3.5 3.5 0.5 4.0 Unit Bits s pF k LSB LSB LSB LSB LSB Note: * Values at maximum operating frequency 289 16.3 MCU Operational Timing This section provides the following timing charts: 16.3.1 16.3.2 16.3.3 16.3.4 16.3.5 16.3.6 16.3.7 Bus Timing Control Signal Timing 16-Bit Free-Running Timer Timing 8-Bit Timer Timing SCI Timing I/O Port Timing External Clock Output Timing Figures 16-4 to 16-5 Figures 16-6 to 16-9 Figures 16-10 to 16-11 Figures 16-12 to 16-14 Figures 16-15 to 16-16 Figure 16-17 Figure 16-18 16.3.1 Bus Timing (1) Basic Bus Cycle (without Wait States) in Expanded Modes T1 t cyc t CH o t AD t Cf t Cr tCL T2 T3 A15 to A0 t ASD t ASI AS, RD t ACC D7 to D0 (read) t AS2 WR tWDD D7 to D0 (write) t WDS t WDH tRDS tRDH t SD t AH t WSD tWSW t SD t AH Figure 16-4 Basic Bus Cycle (without Wait States) in Expanded Modes 290 (2) Basic Bus Cycle (with 1 Wait State) in Expanded Modes T1 o T2 TW T3 A15 to A0 AS, RD D7 to D0 (read) WR D7 to D0 (write) t WTS t WTH t WTS t WTH WAIT Figure 16-5 Basic Bus Cycle (with 1 Wait State) in Expanded Modes 291 16.3.2 Control Signal Timing (1) Reset Input Timing o tRESS RES tRESW tRESS Figure 16-6 Reset Input Timing (2) Interrupt Input Timing o tNMIS NMI IRQE (edge) tNMIH tNMIS IRQL (level) tNMIW NMI IRQi Note: i = 0 to 2; IRQE: IRQi when edge-sensed; IRQL: IRQi when level-sensed Figure 16-7 Interrupt Input Timing 292 (3) Clock Settling Timing o VCC STBY tOSC1 tOSC1 RES Figure 16-8 Clock Settling Timing (4) Clock Settling Timing for Recovery from Software Standby Mode o NMI IRQi (i = 0, 1, 2) tOSC2 Figure 16-9 Clock Settling Timing for Recovery from Software Standby Mode 293 16.3.3 16-Bit Free-Running Timer Timing (1) Free-Running Timer Input/Output Timing o Free-running Compare-match timer counter tFTOD FTOA , FTOB tFTIS FTIA, FTIB, FTIC, FTID Figure 16-10 Free-Running Timer Input/Output Timing (2) External Clock Input Timing for Free-Running Timer o tFTCS FTCI tFTCWL tFTCWH Figure 16-11 External Clock Input Timing for Free-Running Timer 294 16.3.4 8-Bit Timer Timing (1) 8-Bit Timer Output Timing o Timer counter Compare-match tTMOD TMO0, TMO1 Figure 16-12 8-Bit Timer Output Timing (2) 8-Bit Timer Clock Input Timing o tTMCS TMCI0, TMCI1 tTMCWL tTMCWH tTMCS Figure 16-13 8-Bit Timer Clock Input Timing (3) 8-Bit Timer Reset Input Timing o tTMRS TMRI0, TMRI1 Timer counter N H'00 Figure 16-14 8-Bit Timer Reset Input Timing 295 16.3.5 Serial Communication Interface Timing (1) SCI Input/Output Timing tScyc Serial clock (SCK) Transmit data (TxD) tRXS Receive data (RxD) tRXH tTXD Figure 16-15 SCI Input/Output Timing (Synchronous Mode) (2) SCI Input Clock Timing tSCKW SCK tScyc Figure 16-16 SCI Input Clock Timing 296 16.3.6 I/O Port Timing Port read/write cycle T1 o tPRS Port 1 to port 7 (input) tPWD Port 1 to port 7* (output) Note: * Except P46 tPRH T2 T3 Figure 16-17 I/O Port Input/Output Timing 16.3.7 External Clock Output Timing Vcc 2.7V Vm STBY EXTAL o RES toaxr* Figure 16-18 External Clock Output Delay Timing Note: * tDEXT includes RES pulse width tRESW (10 tcyc). 297 298 Appendix A CPU Instruction Set A.1 Instruction Set List Operation Notation Rd8/16 Rs8/16 Rn8/16 CCR N Z V C PC SP #xx:3/8/16 d:8/16 @aa:8/16 + - x / -- General register (destination) (8 or 16 bits) General register (source) (8 or 16 bits) General register (8 or 16 bits) Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data (3, 8, or 16 bits) Displacement (8 or 16 bits) Absolute address (8 or 16 bits) Addition Subtraction Multiplication Division AND logical OR logical Exclusive OR logical Move Not Condition Code Notation * 0 -- Modified according to the instruction result Undetermined (unpredictable) Always cleared to 0 Not affected by the instruction result 299 Table A-1 Instruction Set Addressing Mode/ Instruction Length Operand Size @(d:16, Rn) Mnemonic Operation @(d:8, PC) Condition Code Implied @@aa No. of States @-Rn/@Rn+ @aa: 8/16 #xx: 8/16 @Rn Rn IHNZVC ---- ---- MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @Rs, Rd MOV.B @(d:16, Rs), Rd MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) MOV.B Rs, @-Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd B #xx:8 Rd8 B Rs8 Rd8 B @Rs16 Rd8 B @(d:16, Rs16) Rd8 B @Rs16 Rd8 Rs16+1 Rs16 B @aa:8 Rd8 B @aa:16 Rd8 B Rs8 @Rd16 B Rs8 @(d:16, Rd16) B Rd16-1 Rd16 Rs8 @Rd16 B Rs8 @aa:8 B Rs8 @aa:16 W #xx:16 Rd16 W Rs16 Rd16 W @Rs16 Rd16 W @Rs16 Rd16 Rs16+2 Rs16 W @aa:16 Rd16 W Rs16 @Rd16 W Rd16-2 Rd16 Rs16 @Rd16 W Rs16 @aa:16 W @SP Rd16 SP+2 SP W SP-2 SP Rs16 @SP 2 2 2 4 2 2 4 2 4 2 2 4 4 2 2 4 2 4 2 4 2 4 2 2 0--2 0--2 0--4 0--6 0--6 0--4 0--6 0--4 0--6 0--6 0--4 0--6 0--4 0--2 0--4 0--6 0--6 0--6 0--4 0--6 0--6 0--6 0--6 0--6 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- MOV.W @(d:16, Rs), Rd W @(d:16, Rs16) Rd16 MOV.W @Rs+, Rd MOV.W @aa:16, Rd MOV.W Rs, @Rd MOV.W Rs, @(d:16, Rd) W Rs16 @(d:16, Rd16) MOV.W Rs, @-Rd MOV.W Rs, @aa:16 POP Rd PUSH Rs 300 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length Operand Size @(d:16, Rn) Mnemonic Operation @(d:8, PC) Condition Code Implied @@aa No. of States @-Rn/@Rn+ @aa: 8/16 #xx: 8/16 @Rn Rn I HNZVC MOVFPE @aa:16, Rd MOVTPE Rs, @aa:16 EEPMOV B Not supported B Not supported -- if R4L0 then Repeat @R5 @R6 R5+1 R5 R6+1 R6 R4L-1 R4L Until R4L=0 else next B Rd8+#xx:8 Rd8 B Rd8+Rs8 Rd8 W Rd16+Rs16 Rd16 B Rd8+#xx:8 +C Rd8 B Rd8+Rs8 +C Rd8 W Rd16+1 Rd16 W Rd16+2 Rd16 B Rd8+1 Rd8 B Rd8 decimal adjust Rd8 B Rd8-Rs8 Rd8 W Rd16-Rs16 Rd16 B Rd8-#xx:8 -C Rd8 B Rd8-Rs8 -C Rd8 W Rd16-1 Rd16 W Rd16-2 Rd16 B Rd8-1 Rd8 B Rd8 decimal adjust Rd8 B 0-Rd8 Rd8 B Rd8-#xx:8 B Rd8-Rs8 W Rd16-Rs16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 ------------ ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDX.B #xx:8, Rd ADDX.B Rs, Rd ADDS.W #1, Rd ADDS.W #2, Rd INC.B Rd DAA.B Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBX.B #xx:8, Rd SUBX.B Rs, Rd SUBS.W #1, Rd SUBS.W #2, Rd DEC.B Rd DAS.B Rd NEG.B Rd CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W Rs, Rd -- -- -- -- 2 2 2 2 2 -- ------------ 2 ------------ 2 ---- --* -- -- -- --2 *2 2 2 2 2 -- ------------ 2 ------------ 2 ---- --* -- -- -- --2 *--2 2 2 2 2 -- 301 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length Operand Size @(d:16, Rn) Mnemonic Operation @(d:8, PC) Condition Code Implied @@aa No. of States @-Rn/@Rn+ @aa: 8/16 #xx: 8/16 @Rn Rn IHNZVC MULXU.B Rs, Rd DIVXU.B Rs, Rd B Rd8 x Rs8 Rd16 B Rd16/Rs8 Rd16 (RdH: remainder, RdL: quotient) B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd8 Rd8 B C b7 b0 C b7 b0 0 b7 b0 C b7 b0 0 2 2 2 2 2 -- -- -- -- -- -- 14 -- -- -- -- 14 AND.B #xx:8, Rd AND.B Rs, Rd OR.B #xx:8, Rd OR.B Rs, Rd XOR.B #xx:8, Rd XOR.B Rs, Rd NOT.B Rd SHAL.B Rd ---- 2 ---- ---- 2 ---- ---- 2 2 2 ---- ---- ---- 0--2 0--2 0--2 0--2 0--2 0--2 0--2 2 SHAR.B Rd B 2 ---- 02 SHLL.B Rd B C 2 ---- 02 SHLR.B Rd B 0 2 ---- 0 0 2 ROTXL.B Rd B C b7 b0 C b7 b0 2 ---- 02 ROTXR.B Rd B 2 ---- 02 302 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length Operand Size @-Rn/@Rn+ @(d:16, Rn) Condition Code @(d:8, PC) @aa: 8/16 Implied @@aa Mnemonic Operation No. of States #xx: 8/16 @Rn Rn I HNZVC ROTL.B Rd B C b7 b0 C b7 b0 2 ---- 02 ROTR.B Rd B 2 ---- 02 BSET #xx:3, Rd BSET #xx:3, @Rd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @Rd BSET Rn, @aa:8 BCLR #xx:3, Rd BCLR #xx:3, @Rd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @Rd BCLR Rn, @aa:8 BNOT #xx:3, Rd BNOT #xx:3, @Rd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @Rd BNOT Rn, @aa:8 B (#xx:3 of Rd8) 1 B (#xx:3 of @Rd16) 1 B (#xx:3 of @aa:8) 1 B (Rn8 of Rd8) 1 B (Rn8 of @Rd16) 1 B (Rn8 of @aa:8) 1 B (#xx:3 of Rd8) 0 B (#xx:3 of @Rd16) 0 B (#xx:3 of @aa:8) 0 B (Rn8 of Rd8) 0 B (Rn8 of @Rd16) 0 B (Rn8 of @aa:8) 0 B (#xx:3 of Rd8) (#xx:3 of Rd8) B (#xx:3 of @Rd16) (#xx:3 of @Rd16) B (#xx:3 of @aa:8) (#xx:3 of @aa:8) B (Rn8 of Rd8) (Rn8 of Rd8) B (Rn8 of @Rd16) (Rn8 of @Rd16) B (Rn8 of @aa:8) (Rn8 of @aa:8) 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 303 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length Operand Size @-Rn/@Rn+ @(d:16, Rn) Condition Code @(d:8, PC) @aa: 8/16 Implied @@aa Mnemonic Operation No. of States #xx: 8/16 @Rn Rn IHNZVC BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8 BLD #xx:3, Rd BLD #xx:3, @Rd BLD #xx:3, @aa:8 BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 BAND #xx:3, Rd BAND #xx:3, @Rd BAND #xx:3, @aa:8 BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 BOR #xx:3, Rd BOR #xx:3, @Rd BOR #xx:3, @aa:8 BIOR #xx:3, Rd BIOR #xx:3, @Rd B (#xx:3 of Rd8) Z B (#xx:3 of @Rd16) Z B (#xx:3 of @aa:8) Z B (Rn8 of Rd8) Z B (Rn8 of @Rd16) Z B (Rn8 of @aa:8) Z B (#xx:3 of Rd8) C B (#xx:3 of @Rd16) C B (#xx:3 of @aa:8) C B (#xx:3 of Rd8) C B (#xx:3 of @Rd16) C B (#xx:3 of @aa:8) C B C (#xx:3 of Rd8) B C (#xx:3 of @Rd16) B C (#xx:3 of @aa:8) B C (#xx:3 of Rd8) B C (#xx:3 of @Rd16) B C (#xx:3 of @aa:8) B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 ------ ---- 2 ------ ---- 6 ------ ---- 6 ------ ---- 2 ------ ---- 6 ------ ---- 6 ---------- 2 ---------- 6 ---------- 6 ---------- 2 ---------- 6 ---------- 6 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ---------- 2 ---------- 6 ---------- 6 ---------- 2 ---------- 6 ---------- 6 ---------- 2 ---------- 6 ---------- 6 ---------- 2 ---------- 6 304 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length Operand Size @(d:16, Rn) @aa: 8/16 Mnemonic Operation Branching Condition @(d:8, PC) Condition Code Implied @@aa No. of States @-Rn/@Rn+ #xx: 8/16 @Rn Condition Code I HNZVC BIOR #xx:3, @aa:8 BXOR #xx:3, Rd BXOR #xx:3, @Rd BXOR #xx:3, @aa:8 BIXOR #xx:3, Rd BIXOR #xx:3, @Rd BIXOR #xx:3, @aa:8 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 JMP @Rn JMP @aa:16 JMP @@aa:8 BSR d:8 B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C -- PC PC+d:8 -- PC PC+2 -- If condition -- is true -- then -- PC PC+d:8 -- else next; -- -- -- -- -- -- -- -- -- -- PC Rn16 -- PC aa:16 -- PC @aa:8 -- SP-2 SP PC @SP PC PC+d:8 CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV = 0 NV = 1 Z (NV) = 0 Z (NV) = 1 2 2 4 2 4 Rn 4 ---------- 6 ---------- 2 ---------- 6 ---------- 6 ---------- 2 ---------- 6 ---------- 6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 4 4 4 2 2 ------------ 6 ------------ 8 ------------ 6 305 Table A-1 Instruction Set (cont) Addressing Mode/ Instruction Length (bytes) Operand Size No. of States @-Rn/@Rn+ @(d:16, Rn) @(d:8, PC) @aa: 8/16 #xx: 8/16 Implied @@aa 2 Mnemonic JSR @Rn Operation @Rn Condition Code IHNZVC -- SP-2 SP PC @SP PC Rn16 -- SP-2 SP PC @SP PC aa:16 SP-2 SP PC @SP PC @aa:8 -- PC @SP SP+2 SP -- CCR @SP SP+2 SP PC @SP SP+2 SP -- Transit to sleep mode. B #xx:8 CCR B Rs8 CCR B CCR Rd8 B CCR#xx:8 CCR B CCR#xx:8 CCR B CCR#xx:8 CCR -- PC PC+2 2 2 2 2 2 2 Rn 2 ------------ 6 JSR @aa:16 4 ------------ 8 JSR @@aa:8 ------------ 8 RTS RTE 2 ------------ 8 2 10 SLEEP LDC #xx:8, CCR LDC Rs, CCR STC CCR, Rd ANDC #xx:8, CCR ORC #xx:8, CCR XORC #xx:8, CCR NOP 2 ------------ 2 2 2 2 2 2 ------------ 2 2 ------------ 2 Notes: The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. Set to 1 if decimal adjustment produces a carry; otherwise cleared to 0. The number of states required for execution is 4n+8 (n = value of R4L). These instructions are not supported by the H8/3437 Series. Set to 1 if the divisor is negative; otherwise cleared to 0. Set to 1 if the divisor is zero; otherwise cleared to 0. 306 A.2 Operation Code Map Table A-2 is a map of the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Some pairs of instructions have identical first bytes. These instructions are differentiated by the first bit of the second byte (bit 7 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1. 307 Table A-2 Operation Code Map 8 ADD SUB DEC SUBS INC ADDS MOV CMP 9 A B C D E Low High 0 1 2 3 4 5 6 7 F ADDX SUBX DAA DAS 0 NOP SLEEP STC LDC ORC XORC ANDC LDC SHLL SHLR ROTXL ROTXR NOT 1 OR XOR AND SHAL SHAR ROTL ROTR NEG 2 MOV 3 BVS BPL JMP 4 BRA*2 BRN*2 BHI BLS BCC*2 BCS*2 BNE BEQ BVC BMI BGE BLT BGT JSR MOV*1 BLE 5 MULXU DIVXU RTS BSR RTE BST BNOT BCLR BTS BOR BXOR BAND BIST BLD MOV EEPMOV Bit manipulation instructions BIOR BIXOR BIAND BILD ADD ADDX CMP SUBX OR XOR AND MOV 308 6 BSET 7 8 9 A B C D E F Notes: 1. The MOVFPE and MOVTPE instructions are identical to MOV instructions in the first byte and first bit of the second byte (bits 15 to 7 of the instruction word). The PUSH and POP instructions are identical in machine language to MOV instructions. 2. The BT, BF, BHS, and BLO instructions are identical in machine language to BRA, BRN, BCC, and BCS, respectively. A.3 Number of States Required for Execution The tables below can be used to calculate the number of states required for instruction execution. Table A-3 indicates the number of states required for each cycle (instruction fetch, branch address read, stack operation, byte data access, word data access, internal operation). Table A-4 indicates the number of cycles of each type occurring in each instruction. The total number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I x SI + J x SJ + K x SK + L x SL + M x SM + N x SN Examples: Mode 1 (on-chip ROM disabled), stack located in external memory, 1 wait state inserted in external memory access. 1. BSET #0, @FFC7 From table A-4: I = L = 2, J = K = M = N= 0 From table A-3: SI = 8, SL = 3 Number of states required for execution: 2 x 8 + 2 x 3 =22 JSR @@30 From table A-4: I = 2, J = K = 1, L = M = N = 0 From table A-3: SI = SJ = SK = 8 Number of states required for execution: 2 x 8 + 1 x 8 + 1 x 8 = 32 2. Table A-3. Number of States Taken by Each Cycle in Instruction Execution Execution Status (Instruction Cycle) Instruction fetch Branch address read Stack operation Byte data access Word data access Internal operation SI SJ SK SL SM SN 1 3 6 1 3+m 6 + 2m 1 Access location On-Chip Memory 2 On-Chip Reg. Field 6 External Memory 6 + 2m Notes: m: Number of wait states inserted in access to external device. 309 Table A-4 Number of Cycles in Each Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 1 2 2 2 2 2 2 1 1 Instruction Mnemonic ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDX ADDS.W #1/2, Rd ADDX.B #xx:8, Rd ADDX.B Rs, Rd AND AND.B #xx:8, Rd AND.B Rs, Rd ANDC BAND ANDC #xx:8, CCR BAND #xx:3, Rd BAND #xx:3, @Rd BAND #xx:3, @aa:8 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BCLR BCLR #xx:3, Rd BCLR #xx:3, @Rd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @Rd BCLR Rn, @aa:8 Note: All values left blank are zero. 310 Table A-4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 2 2 2 1 1 2 2 2 2 1 1 1 1 2 2 1 1 1 1 1 1 Instruction Mnemonic BIAND BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 BILD BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BIOR BIOR #xx:3, Rd BIOR #xx:3, @Rd BIOR #xx:3, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @Rd BIXOR #xx:3, @aa:8 BLD BLD #xx:3, Rd BLD #xx:3, @Rd BLD #xx:3, @aa:8 BNOT BNOT #xx:3, Rd BNOT #xx:3, @Rd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @Rd BNOT Rn, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @Rd BOR #xx:3, @aa:8 BSET BSET #xx:3, Rd BSET #xx:3, @Rd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @Rd BSET Rn, @aa:8 Note: All values left blank are zero. 311 Table A-4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 2 1 2 2 1 2 2 1 2 2 1 2 2 1 1 1 1 1 1 1 2 1 2 2 2 2 2 2 1 1 1 1 1 2 1 1 1 1 1 1 1 2 2 2 2n+2* 12 1 1 1 1 1 1 1 2 2 1 Instruction Mnemonic BSR BST BSR d:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BTST BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @Rd BXOR #xx:3, @aa:8 CMP CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W Rs, Rd DAA DAS DEC DIVXU EEPMOV INC JMP DAA.B Rd DAS.B Rd DEC.B Rd DIVXU.B Rs, Rd EEPMOV INC.B Rd JMP @Rn JMP @aa:16 JMP @@aa:8 JSR JSR @Rn JSR @aa:16 JSR @@aa:8 LDC LDC #xx:8, CCR LDC Rs, CCR MOV MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @Rs, Rd MOV.B @(d:16,Rs), Rd Notes: All values left blank are zero. * n: Initial value in R4L. Source and destination are accessed n + 1 times each. 312 Table A-4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 1 1 2 1 1 1 1 1 1 1 1 1 2 2 Instruction Mnemonic MOV MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) 2 MOV.B Rs, @-Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd 1 1 2 2 1 1 1 1 1 1 1 1 1 1 2 2 MOV.W @(d:16, Rs), Rd 2 MOV.W @Rs+, Rd MOV.W @aa:16, Rd MOV.W Rs, @Rd 1 2 1 MOV.W Rs, @(d:16, Rd) 2 MOV.W Rs, @-Rd MOV.W Rs, @aa:16 MOVFPE MOVTPE MULXU NEG NOP NOT OR MOVFPE @aa:16, Rd MOVTPE.Rs, @aa:16 MULXU.Rs, Rd NEG.B Rd NOP NOT.B Rd OR.B #xx:8, Rd OR.B Rs, Rd ORC POP PUSH ROTL ROTR ROTXL ROTXR RTE RTS ORC #xx:8, CCR POP Rd PUSH Rd ROTL.B Rd ROTR.B Rd ROTXL.B Rd ROTXR.B Rd RTE RTS 1 2 Not supported Not supported 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 1 1 1 12 2 2 2 2 Note: All values left blank are zero. 313 Table A-4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation I J K L M N 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Instruction Mnemonic SHAL SHAR SHLL SHLR SLEEP STC SUB SHAL.B Rd SHAR.B Rd SHLL.B Rd SHLR.B Rd SLEEP STC CCR, Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBS SUBX SUBS.W #1/2, Rd SUBX.B #xx:8, Rd SUBX.B Rs, Rd XOR XOR.B #xx:8, Rd XOR.B Rs, Rd XORC XORC #xx:8, CCR Note: All values left blank are zero. 314 Appendix B Internal I/O Register B.1 Addresses Addr. (Last Byte) H'80 H'81 H'82 H'83 H'84 H'85 H'86 H'87 H'88 H'89 H'8A H'8B H'8C H'8D H'8E H'8F H'90 H'91 H'92 H'93 H'94 -- -- -- -- -- -- -- -- TIER TCSR FRCH FRCL OCRAH OCRBH H'95 OCRAL OCRBL H'96 H'97 H'98 H'99 H'9A H'9B H'9C H'9D H'9E H'9F TCR TOCR ICRAH ICRAL ICRBH ICRBL ICRCH ICRCL ICRDH ICRDL (Continued on next page) IEDGA -- IEDGB -- IEDGC -- IEDGD OCRS BUFEA OEA BUFEB OEB CKS1 OLVLA CKS0 OLVLB -- -- -- -- -- -- -- -- ICIAE ICFA -- -- -- -- -- -- -- -- ICIBE ICFB -- -- -- -- -- -- -- -- ICICE ICFC -- -- -- -- -- -- -- -- ICIDE ICFD -- -- -- -- -- -- -- -- OCIAE OCFA -- -- -- -- -- -- -- -- OCIBE OCFB -- -- -- -- -- -- -- -- OVIE OVF -- -- -- -- -- -- -- -- -- CCLRA FRT -- Register Name Bit 7 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module External addresses (in expanded modes) Notes: FRT: Free-running timer 315 (Continued from previous page) Addr. (Last Byte) H'A0 H'A1 H'A2 H'A3 H'A4 H'A5 H'A6 H'A7 H'A8 H'A9 H'AA H'AB H'AC H'AD H'AE H'AF H'B0 H'B1 H'B2 H'B3 H'B4 H'B5 H'B6 H'B7 H'B8 H'B9 H'BA H'BB Bit Names Bit 6 -- -- -- -- -- -- -- -- WT/IT Bit 5 -- -- -- -- -- -- -- -- TME Bit 4 -- -- -- -- -- -- -- -- -- Bit 3 -- -- -- -- -- -- -- -- Bit 2 -- -- -- -- -- -- -- -- Bit 1 -- -- -- -- -- -- -- -- CKS1 Bit 0 -- -- -- -- -- -- -- -- CKS0 WDT Module -- Register Name Bit 7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TCSR/TCNT OVF TCNT -- -- P1PCR P2PCR P3PCR -- P1DDR P2DDR P1DR P2DR P3DDR P4DDR P3DR P4DR P5DDR P6DDR P5DR P6DR -- -- P17PCR P27PCR P37PCR -- P17DDR P27DDR P17 P27 P37DDR P47DDR P37 P47 -- P67DDR -- P67 RST/NMI CKS2 -- -- P16PCR P26PCR P36PCR -- P16DDR P26DDR P16 P26 P36DDR P46DDR P36 P46 -- P66DDR -- P66 -- -- P15PCR P25PCR P35PCR -- P15DDR P25DDR P15 P25 P35DDR P45DDR P35 P45 -- P65DDR -- P65 -- -- P14PCR P24PCR P34PCR -- P14DDR P24DDR P14 P24 P34DDR P44DDR P34 P44 -- P64DDR -- P64 -- -- P13PCR P23PCR P33PCR -- P13DDR P23DDR P13 P23 P33DDR P43DDR P33 P43 -- P63DDR -- P63 -- -- P12PCR P22PCR P32PCR -- P12DDR P22DDR P12 P22 P32DDR P42DDR P32 P42 P52DDR P62DDR P52 P62 -- -- P11PCR P21PCR P31PCR -- P11DDR P21DDR P11 P21 P31DDR P41DDR P31 P41 P51DDR P61DDR P51 P61 -- -- P10PCR P20PCR P30PCR -- P10DDR P20DDR P10 P20 P30DDR P40DDR P30 P40 P50DDR P60DDR P50 P60 -- Port 1 Port 2 Port 3 -- Port 1 Port 2 Port 1 Port 2 Port 3 Port 4 Port 3 Port 4 Port 5 Port 6 Port 5 Port 6 Notes: WDT: Watchdog timer (Continued on next page) 316 (Continued from preceding page) Addr. (Last Byte) H'BC H'BD H'BE H'BF H'C0 H'C1 H'C2 H'C3 H'C4 H'C5 H'C6 H'C7 H'C8 H'C9 H'CA H'CB H'CC H'CD H'CE H'CF H'D0 H'D1 H'D2 H'D3 H'D4 H'D5 H'D6 H'D7 Bit Names Bit 6 -- -- P76 -- -- -- -- -- STS2 -- -- -- CMIEA CMFA Bit 5 -- -- P75 -- -- -- CKDBL -- STS1 -- -- -- OVIE OVF Bit 4 -- -- P74 -- -- -- -- -- STS0 -- -- -- CCLR1 -- Bit 3 -- -- P73 -- -- -- WMS1 -- XRST -- -- -- CCLR0 OS3 Bit 2 -- -- P72 -- -- -- WMS0 MPE NMIEG -- IRQ2SC IRQ2E CKS2 OS2 Bit 1 -- -- P71 -- -- -- WC1 ICKS1 -- MDS1 IRQ1SC IRQ1E CKS1 OS1 Bit 0 -- -- P70 -- -- -- WC0 ICKS0 RAME MDS0 IRQ0SC IRQ0E CKS0 OS0 TMR0 Module -- -- Port 7 -- -- -- System control Register Name Bit 7 -- -- P7PIN -- -- -- WSCR STCR SYSCR MDCR ISCR IER TCR TCSR TCORA TCORB TCNT -- -- -- TCR TCSR TCORA TCORB TCNT -- -- -- -- -- -- -- -- -- CMIEB CMFB -- -- P77 -- -- -- -- -- SSBY -- -- -- CMIEB CMFB -- -- -- CMIEA CMFA -- -- -- OVIE OVF -- -- -- CCLR1 -- -- -- -- CCLR0 OS3 -- -- -- CKS2 OS2 -- -- -- CKS1 OS1 -- -- -- CKS0 OS0 TMR1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- (Continued on next page) Notes: TMR0: 8-bit timer channel 0 TMR1: 8-bit timer channel 1 317 (Continued from preceding page) Addr. (Last Byte) H'D8 H'D9 H'DA H'DB H'DC H'DD H'DE H'DF H'E0 H'E1 H'E2 H'E3 H'E4 H'E5 H'E6 H'E7 H'E8 H'E9 H'EA H'EB H'EC H'ED H'EE H'EF Bit Names Bit 6 CHR Bit 5 PE Bit 4 O/E Bit 3 STOP Bit 2 MP Bit 1 CKS1 Bit 0 CKS0 Module SCI Register Name Bit 7 SMR BRR SCR TDR SSR RDR -- -- -- -- TDRE TIE C/A RIE TE RE MPIE TEIE CKE1 CKE0 RDRF ORER FER PER TEND MPB MPBT -- -- AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE -- -- -- -- -- -- -- -- -- AD7 -- AD7 -- AD7 -- AD7 -- ADST -- -- -- -- -- -- -- -- -- AD6 -- AD6 -- AD6 -- AD6 -- SCAN -- -- -- -- -- -- -- -- -- AD5 -- AD5 -- AD5 -- AD5 -- CKS -- -- -- -- -- -- -- -- -- AD4 -- AD4 -- AD4 -- AD4 -- CH2 -- -- -- -- -- -- -- -- -- AD3 -- AD3 -- AD3 -- AD3 -- CH1 -- -- -- -- -- -- -- -- -- AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- -- -- -- -- -- -- (Continued on next page) -- A/D ADDRAH AD9 ADDRAL AD1 ADDRBH AD9 ADDRBL AD1 ADDRCH AD9 ADDRCL AD1 ADDRDH AD9 ADDRDL AD1 ADCSR ADCR -- -- -- -- -- -- ADF TRGE -- -- -- -- -- -- Notes: A/D: Analog-to-digital converter SCI: Serial communication interface 318 (Continued from preceding page) Addr. (Last Byte) H'F0 H'F1 H'F2 H'F3 H'F4 H'F5 H'F6 H'F7 H'F8 H'F9 H'FA H'FB H'FC H'FD H'FE H'FF Bit Names Bit 6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Module -- Register Name Bit 7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 319 B.2 Function Descriptions Register name Abbreviation of register name Bit No. Initial value Address onto which register is mapped TIER--Timer Interrupt Enable Register Bit Initial value Read/Write 7 ICIAE 0 R/W 6 ICIBE 0 R/W 5 ICICE 0 R/W 4 ICIDE 0 R/W H'FF90 3 2 OCIAE OCIBE 0 0 R/W R/W 1 OVIE 0 R/W FRT 0 -- 1 -- Name of on-chip supporting module Bit names (abbreviations). Bits marked "--" are reserved. Type of access permitted R Read only W Write only R/W Read or write Overflow Interrupt Enable 0 Overflow interrupt request is disabled. 1 Overflow interrupt request is enabled. Output Compare Interrupt B Enable 0 Output compare interrupt request B is disabled. 1 Output compare interrupt request B is enabled. Output Compare Interrupt A Enable 0 Output compare interrupt request A is disabled. 1 Output compare interrupt request A is enabled. Input Capture Interrupt D Enable 0 Input capture interrupt request D is disabled. 1 Input capture interrupt request D is enabled. Full name of bit Description of bit function 320 TIER--Timer Interrupt Enable Register Bit Initial value Read/Write 7 ICIAE 0 R/W 6 ICIBE 0 R/W 5 ICICE 0 R/W 4 ICIDE 0 R/W 3 H'FF90 2 OCIBE 0 R/W 1 OVIE 0 R/W 0 -- 1 -- FRT OCIAE 0 R/W Overflow Interrupt Enable 0 Overflow interrupt request is disabled. 1 Overflow interrupt request is enabled. Output Compare Interrupt B Enable 0 Output compare interrupt request B is disabled. 1 Output compare interrupt request B is enabled. Output Compare Interrupt A Enable 0 Output compare interrupt request A is disabled. 1 Output compare interrupt request A is enabled. Input Capture Interrupt D Enable 0 Input capture interrupt request D is disabled. 1 Input capture interrupt request D is enabled. Input Capture Interrupt C Enable 0 Input capture interrupt request C is disabled. 1 Input capture interrupt request C is enabled. Input Capture Interrupt B Enable 0 Input capture interrupt request B is disabled. 1 Input capture interrupt request B is enabled. Input Capture Interrupt A Enable 0 Input capture interrupt request A is disabled. 1 Input capture interrupt request A is enabled. 321 TCSR--Timer Control/Status Register Bit Initial value Read/Write 7 ICFA 0 R/(W) * 6 ICFB 0 R/(W) * 5 ICFC 0 R/(W) * 4 ICFD 0 R/(W) * 3 H'FF91 2 OCFB 0 R/(W) * 1 OVF 0 R/(W) * 0 FRT OCFA 0 R/(W) * CCLRA 0 R/W Counter Clear A 0 FRC count is not cleared. 1 FRC count is cleared by compare-match A. Timer Overflow Flag 0 Cleared by reading OVF = 1, then writing 0 in OVF. 1 Set when FRC changes from H'FFFF to H'0000. Output Compare Flag B 0 Cleared by reading OCFB = 1, then writing 0 in OCFB. 1 Set when FRC = OCRB. Output Compare Flag A 0 Cleared by reading OCFA = 1, then writing 0 in OCFA. 1 Set when FRC = OCRA. Input Capture Flag D 0 Cleared by reading ICFD = 1, then writing 0 in ICFD. 1 When input capture signal is generated. Input Capture Flag C 0 Cleared by reading ICFC = 1, then writing 0 in ICFC. 1 When input capture signal is generated. Input Capture Flag B 0 Cleared by reading ICFB = 1, then writing 0 in ICFB. 1 Set when FTIB input causes FRC to be copied to ICRB. nput Capture Flag A 0 Cleared by reading ICFA = 1, then writing 0 in ICFA. 1 Set when FTIA input causes FRC to be copied to ICRA. Note: * Software can write a 0 in bits 7 to 1 to clear the flags, but cannot write a 1 in these bits. 322 FRC (H and L)--Free-Running Counter H'FF92, H'FF93 FRT Bit Initial value Read/Write 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Count value OCRA (H and L)--Output Compare Register A H'FF94, H'FF95 FRT Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Continually compared with FRC. OCFA is set to 1 when OCRA = FRC. OCRB (H and L)--Output Compare Register B Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 H'FF94, H'FF95 6 1 5 1 4 1 3 1 2 1 1 1 FRT 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Continually compared with FRC. OCFB is set to 1 when OCRB = FRC. 323 TCR--Timer Control Register Bit Initial value Read/Write 7 IEDGA 0 R/W 6 IEDGB 0 R/W 5 IEDGC 0 R/W 4 IEDGD 0 R/W 3 H'FF96 2 BUFEB 0 R/W 1 CKS1 0 R/W 0 FRT BUFEA 0 R/W CKS0 0 R/W Clock Select 0 0 Internal clock source: oP/2 0 1 Internal clock source: oP/8 1 0 Internal clock source: oP/32 1 1 External clock source: counted on rising edge Buffer Enable B 0 ICRD is used for input capture D. 1 ICRD is buffer register for input capture B. Buffer Enable A 0 ICRC is used for input capture C. 1 ICRC is buffer register for input capture A. Input Edge Select D 0 Falling edge of FTID is valid. 1 Rising edge of FTID is valid. Input Edge Select C 0 Falling edge of FTIC is valid. 1 Rising edge of FTIC is valid. Input Edge Select B 0 Falling edge of FTIB is valid. 1 Rising edge of FTIB is valid. Input Edge Select A 0 Falling edge of FTIA is valid. 1 Rising edge of FTIA is valid. 324 TOCR--Timer Output Compare Control Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 OCRS 0 R/W 3 H'FF97 2 OEB 0 R/W 1 OLVLA 0 R/W 0 FRT OEA 0 R/W OLVLB 0 R/W Output Level B 0 Compare-match B causes 0 output. 1 Compare-match B causes 1 output. Output Level A 0 Compare-match A causes 0 output. 1 Compare-match A causes 1 output. Output Enable B 0 Output compare B output is disabled. 1 Output compare B output is enabled. Output Enable A 0 Output compare A output is disabled. 1 Output compare A output is enabled. Output Compare Register Select 0 The CPU can access OCRA. 1 The CPU can access OCRB. ICRA (H and L)--Input Capture Register A Bit Initial value Read/Write 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R H'FF98, H'FF99 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R FRT 0 0 R Contains FRC count captured on FTIA input. 325 ICRB (H and L)--Input Capture Register B Bit Initial value Read/Write 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R H'FF9A, H'FF9B 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R FRT 0 0 R Contains FRC count captured on FTIB input. ICRC (H and L)--Input Capture Register C Bit Initial value Read/Write 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R H'FF9C, H'FF9D 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R FRT 0 0 R Contains FRC count captured on FTIC input, or old ICRA value in buffer mode. ICRD (H and L)--Input Capture Register D Bit Initial value Read/Write 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R H'FF9E, H'FF9F 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R FRT 0 0 R Contains FRC count captured on FTID input, or old ICRB value in buffer mode. 326 TCSR--Timer Control/Status Register Bit Initial value Read/Write 7 OVF 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 -- 3 H'FFA8 2 CKS2 0 R/W 1 CKS1 0 R/W 0 WDT RST/NMI 0 R/W CKS0 0 R/W Clock Select 2 to 0 0 0 0 oP/2 1 oP/32 1 0 oP/64 1 oP/128 1 0 0 oP/256 1 oP/512 1 0 oP/2048 1 oP/4096 Reset or NMI Select 0 NMI function enabled 1 Reset function enabled Timer Enable 0 Timer disabled: TCNT is initialized to H'00 and stopped 1 Timer enabled: TCNT runs; CPU interrupts can be requested Timer Mode Select 0 Interval timer mode (interval timer interrupt request) 1 Watchdog timer mode (generates reset or NMI signal) Overflow Flag 0 Cleared by reading OVF = 1, then writing 1 in OVF 1 Set when TCNT changes from H'FF to H'00 Note: * Only 0 can be written, to clear the flag. 327 TCNT--Timer Counter H'FFA9 (read), H'FFA8 (write) 6 0 R/W 5 0 R/W 4 0 R/W Count value 3 0 R/W 2 0 R/W 1 0 R/W 0 0 WDT Bit Initial value Read/Write 7 0 R/W R/W P1PCR--Port 1 Input Pull-Up Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'FFAC 2 0 R/W 1 0 R/W 0 0 Port 1 P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR R/W Port 1 Input Pull-Up Control 0 Input pull-up transistor is off. 1 Input pull-up transistor is on. P2PCR--Port 2 Input Pull-Up Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'FFAD 2 0 R/W 1 0 R/W 0 0 Port 2 P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR R/W Port 2 Input Pull-Up Control 0 Input pull-up transistor is off. 1 Input pull-up transistor is on. 328 P3PCR--Port 3 Input Pull-Up Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'FFAE 2 0 R/W 1 0 R/W 0 0 Port 3 P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR R/W Port 3 Input Pull-Up Control 0 Input pull-up transistor is off. 1 Input pull-up transistor is on. P1DDR--Port 1 Data Direction Register Bit Mode 1 Initial value Read/Write Modes 2 and 3 Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 1 -- 1 -- 1 -- 1 -- 1 -- 7 6 5 4 3 H'FFB0 2 1 0 Port 1 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR 1 -- 0 W 1 -- 0 W 1 -- 0 W Port 1 Input/Output Control 0 Input port 1 Output port P1DR--Port 1 Data Register Bit Initial value Read/Write 7 P17 0 R/W 6 P16 0 R/W 5 P15 0 R/W 4 P14 0 R/W 3 P13 0 R/W H'FFB2 2 P12 0 R/W 1 P11 0 R/W 0 Port 1 P10 0 R/W 329 P2DDR--Port 2 Data Direction Register Bit Mode 1 Initial value Read/Write Modes 2 and 3 Initial value Read/Write 0 W 0 W 0 W 0 W 0 W 1 -- 1 -- 1 -- 1 -- 1 -- 7 6 5 4 3 H'FFB1 2 1 0 Port 2 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR 1 -- 0 W 1 -- 0 W 1 -- 0 W Port 2 Input/Output Control 0 Input port 1 Output port P2DR--Port 2 Data Register Bit Initial value Read/Write 7 P27 0 R/W 6 P26 0 R/W 5 P25 0 R/W 4 P24 0 R/W 3 P23 0 R/W H'FFB3 2 P22 0 R/W 1 P21 0 R/W 0 Port 2 P20 0 R/W P3DDR--Port 3 Data Direction Register Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W H'FFB4 2 0 W 1 0 W 0 0 Port 3 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR W Port 3 Input/Output Control 0 Input port 1 Output port 330 P3DR--Port 3 Data Register Bit Initial value Read/Write 7 P37 0 R/W 6 P36 0 R/W 5 P35 0 R/W 4 P34 0 R/W 3 P33 0 R/W H'FFB6 2 P32 0 R/W 1 P31 0 R/W 0 Port 3 P30 0 R/W P4DDR--Port 4 Data Direction Register Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W H'FFB5 2 0 W 1 0 W 0 0 Port 4 P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR W Port 4 Input/Output Control 0 Input port 1 Output port P4DR--Port 4 Data Register Bit Initial value Read/Write 7 P47 0 R/W 6 P46 0 R/W 5 P45 0 R/W 4 P44 0 R/W 3 P43 0 R/W H'FFB7 2 P42 0 R/W 1 P41 0 R/W 0 Port 4 P40 0 R/W P5DDR--Port 5 Data Direction Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- H'FFB8 2 0 W 1 0 W 0 0 Port 5 P52DDR P51DDR P50DDR W Port 5 Input/Output Control 0 Input port 1 Output port 331 P5DR--Port 5 Data Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- H'FFBA 2 P52 0 R/W 1 P51 0 R/W 0 Port 5 P50 0 R/W P6DDR--Port 6 Data Direction Register Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W H'FFB9 2 0 W 1 0 W 0 0 Port 6 P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR W Port 6 Input/Output Control 0 Input port 1 Output port P6DR--Port 6 Data Register Bit Initial value Read/Write 7 P67 0 R/W 6 P66 0 R/W 5 P65 0 R/W 4 P64 0 R/W 3 P63 0 R/W H'FFBB 2 P62 0 R/W 1 P61 0 R/W 0 Port 6 P60 0 R/W P7PIN--Port 7 Input Register Bit Initial value Read/Write 7 P77 * R 6 P76 * R 5 P75 * R 4 P74 * R 3 P73 * R H'FFBE 2 P72 * R 1 P71 * R 0 Port 7 P70 * R Note: * Depends on the levels of pins P77 to P70. 332 WSCR--Wait-State Control Register Bit Initial value Read/Write 7 -- 0 R/W 6 -- 0 R/W 5 CKDBL 0 R/W 4 -- 0 R/W 3 H'FFC2 2 WMS0 0 R/W System Control 1 WC1 0 R/W 0 WC0 0 R/W WMS1 1 R/W Wait Count 0 0 No wait states inserted by wait-state controller 0 1 1 state inserted 1 0 2 states inserted 1 1 3 states inserted Wait Mode Select 0 0 Programmable wait mode 0 1 No wait states inserted by wait-state controller 1 0 Pin wait mode 1 1 Pin auto-wait mode Clock Double 0 Supporting module clock frequency is not divided (oP = o) 1 Supporting module clock frequency is divided by two (oP = o/2) 333 STCR--Serial/Timer Control Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- H'FFC3 2 MPE 0 R/W 1 System Control 0 ICKS0 0 R/W ICKS1 0 R/W Internal Clock Source Select See TCR under TMR0 and TMR1. Multiprocessor Enable 0 Multiprocessor communication function is disabled. 1 Multiprocessor communication function is enabled. 334 SYSCR--System Control Register Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 H'FFC4 2 NMIEG 0 R/W 1 - 1 - System Control 0 RAME 1 R/W XRST 1 R RAM Enable 0 On-chip RAM is disabled. 1 On-chip RAM is disabled. (initial value) NMI Edge 0 Falling edge of NMI is detected. 1 Rising edge of NMI is detected. External Reset 0 Reset was caused by watchdog timer overflow. 1 Reset was caused by external reset signal (initial vaue) Standby Timer Select 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 - - Clock setting time = 8, 192 states (initial value) Clock setting time = 16, 384 states Clock setting time = 32, 7682 states Clock setting time = 65, 536 states Clock setting time = 131, 072 states Disabled Software Standby 0 SLEEP instruction causes transition to sleep mode, (initial value) 1 SLEEP instruction causes transition to software standby mode. 335 MDCR--Mode Control Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 0 -- 3 -- 0 -- H'FFC5 2 -- 1 -- 1 System Control 0 MDS0 * R MDS1 * R Mode Select Bits Value at mode pins. Note: * Determined by inputs at pins MD1 and MD0. ISCR--IRQ Sense Control Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- H'FFC6 2 0 R/W 1 0 System Control 0 0 R/W IRQ2SC IRQ1SC IRQ0SC R/W IRQ0 to IRQ2 Sense Control 0 IRQ0 to IRQ2 are level-sensed (active low). 1 IRQ0 to IRQ2 are edge-sensed (falling edge). IER--IRQ Enable Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- H'FFC7 2 IRQ2E 0 R/W 1 System Control 0 IRQ0E 0 R/W IRQ1E 0 R/W IRQ0 to IRQ2 Enable 0 IRQ0 to IRQ2 are disabled. 1 IRQ0 to IRQ2 are enabled. 336 TCR--Timer Control Register Bit Initial value Read/Write 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W H'FFC8 3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W TMR0 0 CKS0 0 R/W Clock Select TCR 0 0 0 0 0 0 0 1 1 1 1 Counter Clear 0 0 Counter is not cleared. 0 1 Cleared by compare-match A. 1 0 Cleared by compare-match B. 1 1 Cleared on rising edge of external reset input. Timer Overflow Interrupt Enable 0 Overflow interrupt request is disabled. 1 Overflow interrupt request is enabled. Compare-Match Interrupt Enable A 0 Compare-match A interrupt request is disabled. 1 Compare-match A interrupt request is enabled. Compare-Match Interrupt Enable B 0 Compare-match B interrupt request is disabled. 1 Compare-match B interrupt request is enabled. 0 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 STCR -- -- -- -- -- -- -- -- -- -- -- -- 0 1 0 1 0 1 -- -- -- -- CKS2 CKS1 CKS0 ICKS1 ICKS0 Description Timer stopped oP /8 internal clock, falling edge oP /2 internal clock, falling edge oP /64 internal clock, falling edge oP /32 internal clock, falling edge oP /1024 internal clock, falling edge oP /256 internal clock, falling edge Timer stopped External clock, rising edge External clock, falling edge External clock, rising and falling edges 337 TCSR--Timer Control/Status Register H'FFC9 TMR0 Bit Initial value Read/Write 7 CMFB 0 R/(W) *1 6 CMFA 0 R/(W)*1 5 OVF 0 R/(W)*1 4 -- 0 -- 3 OS3 *2 0 R/W 2 OS2 *2 0 R/W 1 OS1*2 0 R/W 0 OS0*2 0 R/W Output Select 0 0 No change on compare-match A. 0 1 Output 0 on compare-match A. 1 0 Output 1 on compare-match A. 1 1 Invert (toggle) output on compare-match A. Output Select 0 0 No change on compare-match B. 0 1 Output 0 on compare-match B. 1 0 Output 1 on compare-match B. 1 1 Invert (toggle) output on compare-match B. Timer Overflow Flag 0 Cleared by reading OVF = 1, then writing 0 in OVF. 1 Set when TCNT changes from H'FF to H'00. Compare-Match Flag A 0 Cleared by reading CMFA = 1, then writing 0 in CMFA. 1 Set when TCNT = TCORA. Compare-Match Flag B 0 Cleared by reading CMFB = 1, then writing 0 in CMFB. 1 Set when TCNT = TCORB. Notes: 1. Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits. 2. When all four bits (OS3 to OS0) are cleared to 0, output is disabled. 338 TCORA--Time Constant Register A Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'FFCA 2 1 R/W 1 1 R/W TMR0 0 1 R/W The CMFA bit is set to 1 when TCORA = TCNT. TCORB--Time Constant Register B Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'FFCB 2 1 R/W 1 1 R/W TMR0 0 1 R/W The CMFB bit is set to 1 when TCORB = TCNT. TCNT--Timer Counter Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W Count value 3 0 R/W H'FFCC 2 0 R/W 1 0 R/W TMR0 0 0 R/W 339 TCR--Timer Control Register Bit Initial value Read/Write 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W H'FFD0 3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W TMR1 0 CKS0 0 R/W Clock Select TCR 0 0 0 0 0 0 0 1 1 1 1 Counter Clear 0 0 Counter is not cleared. 0 1 Cleared by compare-match A. 1 0 Cleared by compare-match B. 1 1 Cleared on rising edge of external reset input. Timer Overflow Interrupt Enable 0 Overflow interrupt request is disabled. 1 Overflow interrupt request is enabled. Compare-Match Interrupt Enable A 0 Compare-match A interrupt request is disabled. 1 Compare-match A interrupt request is enabled. Compare-Match Interrupt Enable B 0 Compare-match B interrupt request is disabled. 1 Compare-match B interrupt request is enabled. 0 0 0 1 1 1 1 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 STCR -- 0 1 0 1 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CKS2 CKS1 CKS0 ICKS1 ICKS0 Description Timer stopped oP /8 internal clock, falling edge oP /2 internal clock, falling edge oP /64 internal clock, falling edge oP /128 internal clock, falling edge oP /1024 internal clock, falling edge oP /2048 internal clock, falling edge Timer stopped External clock, rising edge External clock, falling edge External clock, rising and falling edges 340 TCSR--Timer Control/Status Register Bit Initial value Read/Write 7 CMFB 0 R/(W) *1 6 CMFA 0 R/(W) *1 5 OVF 0 R/(W) *1 4 -- 1 -- 3 H'FFD1 2 OS2 *2 0 R/W 1 OS1*2 0 R/W TMR1 0 OS0*2 0 R/W OS3*2 0 R/W Notes: Bit functions are the same as for TMR0. 1. Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits. 2. When all four bits (OS3 to OS0) are cleared to 0, output is disabled. TCORA--Time Constant Register A Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'FFD2 2 1 R/W 1 1 R/W TMR1 0 1 R/W Note: Bit functions are the same as for TMR0. TCORB--Time Constant Register B Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'FFD3 2 1 R/W 1 1 R/W TMR1 0 1 R/W Note: Bit functions are the same as for TMR0. TCNT--Timer Counter Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W H'FFD4 2 0 R/W 1 0 R/W TMR1 0 0 R/W Note: Bit functions are the same as for TMR0. 341 SMR--Serial Mode Register Bit Initial value Read/Write 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 H'FFD8 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SCI STOP 0 R/W Clock Select 0 0 o clock 0 1 oP /4 clock 1 0 oP /16 clock 1 1 oP /64 clock Multiprocessor Mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop Bit Length 0 One stop bit 1 Two stop bits Parity Mode 0 Even parity 1 Odd parity Parity Enable 0 Transmit: No parity bit added. Receive: Parity bit not checked. 1 Transmit: Parity bit added. Receive: Parity bit checked. Character Length 0 8-bit data length 1 7-bit data length Communication Mode 0 Asynchronous 1 Synchronous 342 BRR--Bit Rate Register Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W H'FFD9 2 1 R/W 1 1 R/W 0 1 R/W SCI Constant that determines the bit rate 343 SCR--Serial Control Register H'FFDA SCI Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Clock Enable 0 0 Asynchronous serial clock not output 1 Asynchronous serial clock output at SCK pin Clock Enable 1 0 Internal clock 1 External clock Transmit End Interrupt Enable 0 TSR-empty interrupt request is disabled. 1 TSR-empty interrupt request is enabled. Multiprocessor Interrupt Enable 0 Multiprocessor receive interrupt function is disabled. 1 Multiprocessor receive interrupt function is enabled. Receive Enable 0 Receive disabled 1 Receive enabled Transmit Enable 0 Transmit disabled 1 Transmit enabled Receive Interrupt Enable 0 Receive interrupt and receive error interrupt requests are disabled. 1 Receive interrupt and receive error interrupt requests are enabled. Transmit Interrupt Enable 0 TDR-empty interrupt request is disabled. 1 TDR-empty interrupt request is enabled. 344 TDR--Transmit Data Register Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W Transmit data 3 1 R/W H'FFDB 2 1 R/W 1 1 R/W 0 1 R/W SCI 345 SSR--Serial Status Register Bit Initial value Read/Write 7 TDRE 1 R/(W) * 6 RDRF 0 R/(W) * 5 ORER 0 R/(W) * 4 FER 0 R/(W) * 3 H'FFDC 2 TEND 1 R 1 MPB 0 R 0 SCI PER 0 R/(W) * MPBT 0 R/W Multiprocessor Bit Transfer 0 Multiprocessor bit = 0 in transmit data. 1 Multiprocessor bit = 1 in transmit data. Multiprocessor Bit 0 Multiprocessor bit = 0 in receive data. 1 Multiprocessor bit = 1 in receive data. Transmit End 0 Cleared by reading TDRE = 1, then writing 0 in TDRE. 1 Set to 1 when TE = 0, or when TDRE = 1 at the end of character transmission. Parity Error 0 Cleared by reading PER = 1, then writing 0 in PER. 1 Set when a parity error occurs (parity of receive data does not match parity selected by O/E bit in SMR). Framing Error 0 Cleared by reading FER = 1, then writing 0 in FER. 1 Set when a framing error occurs (stop bit is 0). Overrun Error 0 Cleared by reading ORER = 1, then writing 0 in ORER. 1 Set when an overrun error occurs (next data is completely received while RDRF bit is set to 1). Receive Data Register Full 0 Cleared by reading RDRF = 1, then writing 0 in RDRF. 1 Set when one character is received normally and transferred from RSR to RDR. Transmit Data Register Empty 0 Cleared by reading TDRE = 1, then writing 0 in TDRE. 1 Set when: 1. Data is transferred from TDR to TSR. 2. TE is cleared while TDRE = 0. Note: * Software can write a 0 in bits 7 to 3 to clear the flags, but cannot write a 1 in these bits. 346 RDR--Receive Data Register Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R Receive data 3 0 R H'FFDD 2 0 R 1 0 R 0 0 R SCI 347 ADDRA (H and L)--A/D Data Register A Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 H'FFE0, H'FFE1 6 5 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 A/D AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R -- 0 R ADDRAH ADDRAL A/D Conversion Data 10-bit data giving an A/D conversion result Reserved Bits ADDRB (H and L)--A/D Data Register B Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 H'FFE2, H'FFE3 6 5 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R A/D 0 -- 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R ADDRBH ADDRBL A/D Conversion Data 10-bit data giving an A/D conversion result Reserved Bits 348 ADDRC (H and L)--A/D Data Register C Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 H'FFE4, H'FFE5 6 5 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 A/D AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R -- 0 R ADDRCH ADDRCL A/D Conversion Data 10-bit data giving an A/D conversion result Reserved Bits ADDRD (H and L)--A/D Data Register D Bit Initial value Read/Write 15 14 13 12 11 10 9 8 7 H'FFE6, H'FFE7 6 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 A/D AD9 AD8 0 R 0 R AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R -- 0 R ADDRDH ADDRDL A/D Conversion Data 10-bit data giving an A/D conversion result Reserved Bits 349 ADCSR--A/D Control/Status Register Bit Initial value Read/Write 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W H'FFE8 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 A/D CH0 0 R/W Channel Select CH2 CH1 0 0 1 1 0 1 CH0 0 1 0 1 0 1 0 1 Single Mode AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Scan Mode AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 Clock Select 0 Conversion time = 266 states (max) 1 Conversion time = 134 states (max) Note: When oP = o Scan Mode 0 Single mode 1 Scan mode A/D Start 0 A/D conversion is halted. 1 1. Single mode: One A/D conversion is performed, then this bit is automatically cleared to 0. 2. Scan mode: A/C conversion starts and continues cyclically on all selected channels until 0 is written in this bit. A/D Interrupt Enable 0 The A/D interrupt request (ADI) is disabled. 1 The A/D interrupt request (ADI) is enabled. A/D End Flag 0 Cleared from 1 to 0 when CPU reads ADF = 1, then writes 0 in ADF. 1 Set to 1 at the following times: 1. Single mode: at the completion of A/D conversion 2. Scan mode: when all selected channels have been converted. Note: * Only 0 can be written, to clear the flag. 350 ADCR--A/D Control Register Bit Initial value Read/Write 7 TRGE 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- H'FFE9 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- A/D Trigger Enable 0 ADTRG is disabled. 1 ADTRG is enabled. A/D conversion can be started by external trigger, or by software. 351 Appendix C I/O Port Block Diagrams C.1 Port 1 Block Diagram Reset R Q D P1nPCR C RP1P Hardware standby WP1P Mode 1 Reset SR Q D P1nDDR C * WP1D Mode 3 Reset R Q D P1nDR C Modes 1 or 2 WP1 P1n RP1 WP1P: Write to P1PCR WP1D: Write to P1DDR WP1: Write to port 1 RP1P: Read P1PCR RP1: Read port 1 n = 0 to 7 Note: * Set priority Figure C-1 Port 1 Block Diagram 352 Internal address bus Internal data bus C.2 Port 2 Block Diagram Reset R Q D P2nPCR C Internal data bus RP2P Hardware standby WP2P Mode 1 Reset SR Q D P2nDDR C * WP2D Mode 3 Reset R Q D P2nDR C WP2 P2n Modes 1 or 2 RP2 WP2P: Write to P2PCR WP2D: Write to P2DDR WP2: Write to port 2 RP2P: Read P2PCR RP2: Read port 2 n = 0 to 7 Note: * Set priority Figure C-2 Port 2 Block Diagram 353 Internal address bus C.3 Port 3 Block Diagram Mode 3 Reset Internal data bus R Q D P3n PCR C WP3P RP3P Mode 3 Reset R Q D P3n DDR C WP3D External address write Mode 3 Reset R D Q P3n DR C P3n Mode 1 or 2 WP3 RP3 External address read WP3P: Write to P3PCR WP3D: Write to P3DDR WP3: Write to Port 3 RP3P : Read P3PCR Read Port 3 RP3: n = 0 to 7 Figure C-3 Port 3 Block Diagram 354 C.4 Port 4 Block Diagrams Reset R Q D 0 P4. DDR C WP4D Reset P40 R Q D P40 DR C WP4 RP4 A/D converter module ADTRG IRQ2 input WP4D: Write to P4DDR WP4: Write to Port 4 RP4: Read Port 4 IRQ enable register IRQ2 enable Schmitt input Figure C-4 (a) Port 4 Block Diagram (Pin P40) 355 Internal data bus Reset R Q D P4n DDR C WP4D Reset P4n R D Q P4n DR C WP4 RP4 Schmitt input IRQ0 input IRQ1 input WP4D: Write to P4DDR WP4: Write to Port 4 Read Port 4 RP4: n = 1, 2 IRQ enable register IRQ0 enable IRQ1 enable Figure C-4 (b) Port 4 Block Diagram (Pins P41and P42) 356 Internal data bus Hardware standby Mode 1 or 2 Reset R Q D P4n DDR C Mode 3 WP4D Reset R Q D P4n DR C P4 n Mode 1 or 2 Internal data bus WP4 RD output WR output AS ouput RP4 WP4D: Write to P4DDR WP4: Write to Port 4 Read Port 4 RP4: n = 3, 4, 5 Figure C-4 (c) Port 4 Block Diagram (Pins P43 to P45) 357 Hardware standby Mode 1 or 2 Reset R S Q D P46 DDR * C WP4D P46 Internal data bus O RP4 WP4D: Write to P4DDR WP4: Write to Port 4 Read Port 4 RP4: Note: * Set-priority Figure C-4 (d) Port 4 Block Diagram (Pin P46) 358 Reset R Q D P47 DDR C WP4D Reset P47 R Q D P47 DR C WP4 RP4 Internal data bus WAIT input WAIT input enable Mode 1 or 2 WP4D: Write to P4DDR WP4: Write to Port 4 RP4: Read Port 4 Figure C-4 (e) Port 4 Block Diagram (Pin P47) 359 C.5 Port 5 Block Diagrams R Q D P50DDR C WP5D Reset P50 R Q D P50DR C WP5 Output enable Serial transmit data RP5 WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 Figure C-5 (a) Port 5 Block Diagram (Pin P50) 360 Internal data bus SCI Reset Reset R Q D P51DDR C WP5D Reset P51 R Q D P51DR C WP5 Internal data bus SCI Input enable Serial receive data RP5 WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 Figure C-5 (b) Port 5 Block Diagram (Pin P51) 361 Reset R Q D P52DDR C WP5D Reset P52 R Q D P52DR C WP5 Internal data bus SCI Clock input enable Clock output enable Clock output Clock input RP5 WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 Figure C-5 (c) Port 5 Block Diagram (Pin P52) 362 C.6 Port 6 Block Diagrams Reset R Q D P60 DDR C WP6D Reset P60 R Q D P60 DR C WP6 Schmitt input RP6 Internal data bus Free-running timer module Counter clock input 8-bit timer module Counter clock input WP6D: Write to P6DDR WP6: Write to Port 6 RP6: Read Port 6 Figure C-6 (a) Port 6 Block Diagram (Pin P60) 363 Reset R Q D P61 DDR C WP6D Reset R Q D P6 1 DR C WP6 P61 Internal data bus Free-running timer module Output enable Output-compare output Schmitt input RP6 WP6D: Write to P6DDR WP6: Write to Port 6 RP6: Read Port 6 Figure C-6 (b) Port 6 Block Diagram (Pin P61) 364 Reset R Q D P62 DDR C WP6D Reset P62 R Q D P62 DR C WP6 Schmitt input RP6 Internal data bus Free-running timer module Input-capture input WP6D: Write to P6DDR WP6: Write to Port 6 RP6: Read Port 6 Figure C-6 (c) Port 6 Block Diagram (Pin P62) 365 Reset R Q D P6n DDR C WP6D Reset P6n R D Q P6n DR C WP6 Schmitt input RP6 Free-running timer module Input-capture input 8-bit timer module Counter clock input Counter reset input WP6D: Write to P6DDR WP6: Write to Port 6 Read Port 6 RP6: n = 3, 5 Figure C-6 (d) Port 6 Block Diagram (Pins P63 and P65) 366 Internal data bus Reset R Q D P64 DDR C WP6D Reset R Q D P6 4 DR C WP6 P64 Internal data bus 8-bit timer module Output enable 8-bit timer output Free-running timer module Input-capture input Schmitt input RP6 WP6D: Write to P6DDR WP6: Write to Port 6 RP6: Read Port 6 Figure C-6 (e) Port 6 Block Diagram (Pin P64) 367 Reset R Q D P66 DDR C WP6D Reset R Q D P6 6 DR C WP6 P66 Internal data bus Free-running timer module Output enable Output-compare output 8-bit timer module Counter reset input Schmitt input RP6 WP6D: Write to P6DDR WP6: Write to Port 6 RP6: Read Port 6 Figure C-6 (f) Port 6 Block Diagram (Pin P66) 368 Reset R Q D P67 DDR C WP6D Reset R Q D P6 7 DR C WP6 P67 Internal data bus 8-bit timer module Output enable 8-bit timer output Schmitt input RP6 WP6D: Write to P6DDR WP6: Write to Port 6 RP6: Read Port 6 Figure C-6 (g) Port 6 Block Diagram (Pin P67) 369 C.7 Port 7 Block Diagrams Internal data bus RP7 P7n A/D converter module Analog input RP7: Read port 7 n = 0 to 7 Figure C-7 Port 7 Block Diagram 370 Appendix D Pin States D.1 Port States in Each Mode Table D-1 Port States Pin Name P17 to P10 A7 to A0 Mode 1 2 Reset Low 3-state Hardware Standby 3-state Software Standby Low Low if DDR = 1, prev. state if DDR = 0 Prev. state Low 3-state 3-state Low Low if DDR = 1, prev. state if DDR = 0 Prev. state 3-state 3-state 3-state 3-state Prev. state (Addr. output pins: last address accessed) Sleep Mode Prev. state (Addr. output pins: last address accessed Normal Operation A7 to A0 Addr. output or input port 3 P27 to P20 A15 to A8 1 2 I/O port A15 to A8 Addr. output or input port 3 P37 to P30 D7 to D0 P47/WAIT 1 2 3 1 2 3 P46/o 1 2 3 Clock output 3-state 3-state 3-state 3-state I/O port D7 to D0 I/O port WAIT / I/O port Prev. state 3-state / Prev. state Prev. state High Prev. state 3-state / Prev. state Prev. state Clock output Clock output if DDR = 1, 3-state if DDR = 0 I/O port Clock output Clock output if DDR = 1, input port if DDR = 0 High if DDR = 1, 3-state if DDR = 0 Notes: 1. 3-state: High-impedance state 2. Prev. state: Previous state. Input ports are in the high-impedance state (with the MOS pull-up on if PCR = 1). Output ports hold their previous output level. 3. I/O port: Direction depends on the data direction (DDR) bit. Note that these pins may also be used by the on-chip supporting modules. See section 7, I/O Ports, for further information. * On-chip supporting modules are initialized, so these pins revert to I/O ports according to the DDR and DR bits. 371 Table D-1 Port States (cont) Pin Name Mode Reset High Hardware Standby 3-state Software Standby High Sleep Mode High Normal Operation AS, WR, RD P45 to P43, 1 AS, WR, RD 2 3 P42 to P40 1 2 3 P52 to P50 1 2 3 P67 to P60 1 2 3 P77 to P70 1 2 3 3-state 3-state 3-state Prev. state Prev. state Prev. state Prev. state I/O port I/O port 3-state 3-state Prev. state* Prev. state I/O port 3-state 3-state Prev. state* Prev. state I/O port 3-state 3-state 3-state 3-state Input port Notes: 1. 3-state: High-impedance state 2. Prev. state: Previous state. Input ports are in the high-impedance state (with the MOS pull-up on if PCR = 1). Output ports hold their previous output level. 3. I/O port: Direction depends on the data direction (DDR) bit. Note that these pins may also be used by the on-chip supporting modules. See section 7, I/O Ports, for further information. * On-chip supporting modules are initialized, so these pins revert to I/O ports according to the DDR and DR bits. 372 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents when the RAME bit in SYSCR is set to 1, drive the RES signal low 10 system clock cycles before the STBY signal goes low, as shown below. RES must remain low until STBY goes low (minimum delay from STBY low to RES high: 0 ns). STBY t1 10 tcyc RES t2 0 ns (2) When the RAME bit in SYSCR is cleared to 0 or when it is not necessary to retain RAM contents, RES does not have to be driven low as in (1). Timing of Recovery From Hardware Standby Mode: Drive the RES signal low approximately 100 ns before STBY goes high. STBY t 100 ns RES tOSC 373 Appendix F Product Code Lineup Table F-1 H8/3297 Series Product Code Lineup Product Type H8/3297 ZTAT version Product Code Standard HD6473297C16 products HD6473297P16 HD6473297F16 HD6473297TF16 Mask ROM version Standard HD6433297P products HD6433297F HD6433297TF H8/3296 Mask ROM version Standard HD6433296P products HD6433296F HD6433296TF Mark Code HD6473297C16 HD6473297P16 HD6473297F16 HD6473297TF16 HD6433297(***)P HD6433297(***)F HD6433297(***)TF HD6433296(***)P HD6433296(***)F HD6433296(***)TF Package (Hitachi Package Code) 64-pin window shrink DIP (DC-64S) 64-pin shrink DIP (DP-64S) 64-pin QFP (FP-64A) 80-pin TQFP (TFP-80C) 64-pin shrink DIP (DC-64S) 64-pin QFP (FP64A) 80-pin TQFP (TFP-80C) 64-pin shrink DIP (DP-64S) 64-pin QFP (FP-64A) 80-pin TQFP (TFP-80C) Notes: (***) in mask ROM versions is the ROM code. 374 Table F-1 H8/3297 Series Product Code Lineup (cont) Product Type H8/3294* ZTAT version Product Code Standard HD6473294P16 products HD6473294F16 HD6473294TF16 Mask ROM version Standard HD6433294P products HD6433294F HD6433294TF H8/3292 Mask ROM version Standard HD6433292P products HD6433292F HD6433292TF Mark Code HD6473294P16 HD6473294F16 HD6473294TF16 HD6433294(***)P HD6433294(***)F HD6433294(***)TF HD6433292(***)P HD6433292(***)F HD6433292(***)TF Package (Hitachi Package Code) 64-pin shrink DIP (DP-64S) 64-pin QFP (FP-64A) 80-pin TQFP (TFP-80C) 64-pin shrink DIP (DP-64S) 64-pin QFP (FP64A) 80-pin TQFP (TFP-80C) 64-pin shrink DIP (DP-64S) 64-pin QFP (FP-64A) 80-pin TQFP (TFP-80C) Notes: (***) in mask ROM versions is the ROM code. 375 Appendix G Package Dimensions Figure G-1 shows the dimensions of the DC-64S package. Figure G-2 shows the dimensions of the DP-64S package. Figure G-3 shows the dimensions of the FP-64A package. Figure G-4 shows the dimensions of the TFP-80C package. Unit: mm 57.30 64 33 18.92 1 1.50 Max 0.9 32 2.54 Min 5.60 Max 19.05 0.51 Min 1.78 0.25 0.48 0.10 0.11 0.25 + 0.05 - Figure G-1 Package Dimensions (DC-64S) Unit: mm 64 57.6 58.5 Max 33 17.0 18.6 Max 1 1.46 Max 1.0 32 2.54 Min 5.08 Max 19.05 0.51 Min 1.78 0.25 0.48 0.10 0.25 - 0.05 0 - 15 + 0.11 Figure G-2 Package Dimensions (DP-64S) 376 Unit: mm 17.2 0.3 14 48 49 17.2 0.3 33 32 0.8 64 1 0.37 0.08 0.35 0.06 16 17 3.05 Max 0.15 M 0.17 0.05 0.15 0.04 2.70 1.0 1.6 0 - 8 0.8 0.3 0.10 Dimension including the plating thickness Base material dimension Figure G-3 Package Dimensions (FP-64A) Unit: mm 14.0 0.2 12 60 61 14.0 0.2 41 40 Unit: mm 80 1 0.22 0.05 0.20 0.04 20 21 0.5 1.20 Max 0.10 +0.15 -0.10 0.10 M 1.25 1.00 0.17 0.05 0.15 0.04 1.0 0 - 8 0.5 0.1 0.10 Dimension including the plating thickness Base material dimension Figure G-4 Package Dimensions (TFP-80C) 0.10 0.10 377 H8/3297 Series Hardware Manual Publication Date: 1st Edition, October 1994 3rd Edition, September 1997 Published by: Semiconductor and IC Div. Hitachi, Ltd. Edited by: Technical Documentation Center Hitachi, Microcomputer System Ltd. Copyright (c) Hitachi, Ltd., 1994. All rights reserved. Printed in Japan. |
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